Worked examples — CISC vs RISC philosophies

This page is the hands-on companion to CISC vs RISC philosophies. There we built the philosophy; here we compute it. Every example nails one cell of the matrix below, so that by the end there is no CISC-vs-RISC arithmetic question an exam can throw that you have not already seen worked.

Before we touch a single number, let us re-anchor the one tool everything rests on.

We will lean on this constantly, so let's picture it once.

Read the figure as a volume: $N$ is the depth, $\text{CPI}$ the width, $T_c$ the height, and CPU time is the box they enclose. Grow one edge and shrink two, and the box can still shrink — that is why RISC can afford to grow $N$ if it shrinks CPI and $T_c$ harder. The number under each box is its volume = the CPU time.

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The scenario matrix

Every CISC-vs-RISC computation you will ever be asked lives in one of these cells. Each row is a case class; the last column names the example that covers it.

#	Case class	What makes it tricky	Covered by
A	RISC wins (the "normal" bet pays off)	more $N$, but CPI + $T_c$ dominate	Example 1
B	CISC wins (the bet fails)	when RISC's $N$ blow-up is too big	Example 2
C	Exact tie	boundary — neither is faster	Example 3
D	Mixed units ($T_c$ vs frequency $f$)	you're given GHz, not ns	Example 4
E	Degenerate: $\text{CPI}=1$ everywhere	limiting "ideal RISC"	Example 5
F	Zero / pathological input	$N=0$, or a stall makes CPI blow up	Example 6
G	Real-world word problem	translate English → the equation	Example 7
H	Exam twist: solve for the unknown	given the answer, find a factor	Example 8
I	Instruction-count from code (μop expansion)	count RISC lines vs one CISC line	Example 9

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Example 1 — Cell A: the RISC bet pays off

Step 1 — Compute CISC time. $T_{\text{CISC}}=1.0\times 10^6\times 4.0\times 1.25\text{ ns}=5.0\times 10^6\text{ ns}=5.0\text{ ms}$ Why this step? We just apply the one equation — no shortcuts. We convert to milliseconds at the end so the two numbers are comparable at a glance ($1\text{ ms}=10^6\text{ ns}$, so we move the decimal 6 places).

Step 2 — Compute RISC time. $T_{\text{RISC}}=1.5\times 10^6\times 1.1\times 1.0\text{ ns}=1.65\times 10^6\text{ ns}=1.65\text{ ms}$ Why this step? Same equation, RISC's numbers. Notice the bigger first factor but smaller other two. Again $1.65\times 10^6\text{ ns}=1.65\text{ ms}$ via the same $10^6$ conversion.

Step 3 — Take the ratio (slower on top). $\frac{T_{\text{CISC}}}{T_{\text{RISC}}}=\frac{5.0}{1.65}\approx 3.03$ Why this step? "By what factor" is answered by a ratio, not a difference — it tells us how many times faster, independent of units. We put CISC (the slower, bigger time) on top so the answer reads "RISC is 3.03× faster."

Recall Verify

Units: $\text{count}\times \text{(cycles/instr)}\times \text{(ns/cycle)}=\text{ns}$ ✓. RISC is $\approx 3\times$ faster despite 50% more instructions — the extra $N$ was crushed by the $3.6\times$ CPI drop and $1.25\times$ cycle-time drop. This is the whole RISC argument in one ratio.

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Example 2 — Cell B: the bet fails, CISC wins

Step 1 — CISC time. $T_{\text{CISC}}=0.5\times 10^6\times 6.0\times 1.0\text{ ns}=3.0\times 10^6\text{ ns}=3.0\text{ ms}$ Why this step? Same equation. CISC's high CPI is its weakness — but watch its tiny $N$. Convert: $3.0\times 10^6\text{ ns}=3.0\text{ ms}$.

Step 2 — RISC time. $T_{\text{RISC}}=6.0\times 10^6\times 1.0\times 0.9\text{ ns}=5.4\times 10^6\text{ ns}=5.4\text{ ms}$ Why this step? RISC's $N$ exploded 12× because one CISC string instruction needed a whole software loop. That is more than its CPI/$T_c$ advantage can repay. Convert: $5.4\times 10^6\text{ ns}=5.4\text{ ms}$.

Step 3 — Ratio (slower on top). $\frac{T_{\text{RISC}}}{T_{\text{CISC}}}=\frac{5.4}{3.0}=1.8$ Why this step? Here RISC is the slower one, so RISC's time goes on top; the result $1.8$ reads "RISC is 1.8× slower than CISC." Always place the bigger time on top so the factor is $>1$.

Recall Verify

RISC is 1.8× slower here. The lesson: RISC's bet is a bet, not a law. When a workload maps onto exactly the specialised instruction CISC provides (string moves, REP MOVSB on x86), the $N$ blow-up can overwhelm everything. This is why modern RISC ISAs added richer extensions — see x86 vs ARM.

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Example 3 — Cell C: the exact tie

Step 1 — CISC time. $T_{\text{CISC}}=2.0\times 10^6\times 3.0\times 1.0\text{ ns}=6.0\times 10^6\text{ ns}=6.0\text{ ms}$ Why this step? We start with CISC because we always compute both raw times first, then compare. Convert to ms with the $10^6$ rule so the two are read on the same scale: $6.0\times 10^6\text{ ns}=6.0\text{ ms}$.

Step 2 — RISC time. $T_{\text{RISC}}=3.0\times 10^6\times 2.0\times 1.0\text{ ns}=6.0\times 10^6\text{ ns}=6.0\text{ ms}$ Why this step? Same equation for RISC. The products land on the same number — both give $6.0\text{ ms}$ after the identical $10^6$ conversion, which is the whole point of this boundary case.

Step 3 — Ratio (either on top). $\frac{T_{\text{CISC}}}{T_{\text{RISC}}}=\frac{6.0}{6.0}=1.00$ Why this step? When neither is slower, the ratio is exactly $1$ whichever time we put on top — the unambiguous fingerprint of a tie.

Recall Verify

Ratio $=1.00$ → dead tie. This is the boundary case: RISC's $\times 1.5$ on $N$ exactly cancels its $\times \frac{2}{3}$ on CPI ($1.5\times \frac{2}{3}=1$). Boundary cases like this prove the equation is a genuine trade-off surface, not a one-sided win.

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Example 4 — Cell D: given frequency, not cycle time

Step 1 — Convert frequency to cycle time. The clock frequency $f$ counts ticks per second; the cycle time is just its reciprocal, because "seconds per tick" is the flip of "ticks per second": $T_c=\frac{1}{f}.$ $T_{c,\text{CISC}}=\frac{1}{2.0\times 10^9\text{ Hz}}=0.5\text{ ns},T_{c,\text{RISC}}=\frac{1}{2.5\times 10^9\text{ Hz}}=0.4\text{ ns}.$ Why this step? The equation needs seconds per cycle; the problem handed us cycles per second. We must flip it first or every unit downstream is wrong. This is the single most common exam trap.

Step 2 — CISC time. $T_{\text{CISC}}=1.0\times 10^6\times 5.0\times 0.5\text{ ns}=2.5\times 10^6\text{ ns}=2.5\text{ ms}$ Why this step? Now that $T_c$ is in nanoseconds, we can multiply the three factors as usual. Convert the result with the $10^6$ rule: $2.5\times 10^6\text{ ns}=2.5\text{ ms}$.

Step 3 — RISC time. $T_{\text{RISC}}=1.4\times 10^6\times 1.2\times 0.4\text{ ns}=0.672\times 10^6\text{ ns}=0.672\text{ ms}$ Why this step? Same equation with RISC's converted $T_c$. We keep the same units (ns) for both machines so the comparison is apples-to-apples; then convert: $0.672\times 10^6\text{ ns}=0.672\text{ ms}$.

Step 4 — Ratio (slower on top). $\frac{T_{\text{CISC}}}{T_{\text{RISC}}}=\frac{2.5}{0.672}\approx 3.72$ Why this step? CISC is the slower machine here, so its time goes on top; $3.72>1$ reads directly as "RISC is 3.72× faster." A ratio also cancels the shared ms unit, leaving a pure number.

Recall Verify

$\text{Hz}=1/\text{s}$, so $1/\text{Hz}=\text{s}$ ✓ — the reciprocal genuinely produces a time. RISC $\approx 3.7\times$ faster. If you had forgotten to flip GHz and plugged $2.0$ and $2.5$ directly as if they were times, every answer would be off by a factor of $10^{18}$ — the units are your alarm bell.

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Example 5 — Cell E: the ideal-RISC limit, $\text{CPI}=1$

Step 1 — Cycle time. $T_c=\frac{1}{3.0\times 10^9}=0.\overline{3}\text{ ns}\approx 0.3333\text{ ns}$ Why this step? Frequency → time, same reciprocal as before, because the equation demands seconds per cycle.

Step 2 — Total time at the CPI floor. $T=3.0\times 10^6\times 1.0\times 0.3333\text{ ns}=1.0\times 10^6\text{ ns}=1.0\text{ ms}$ Why this step? With $\text{CPI}=1$, the middle factor multiplies by 1 and effectively disappears — time collapses to $N\times T_c$, i.e. exactly one tick per instruction. We compute it explicitly to see that collapse, then convert $1.0\times 10^6\text{ ns}=1.0\text{ ms}$. This is the limiting best case a single-issue pipeline can reach; you cannot go below CPI $=1$ without issuing more than one instruction per cycle (superscalar, out of scope here). See Pipelining.

Recall Verify

$N\times T_c=3.0\times 10^6\times 0.3333\text{ ns}=1.0\text{ ms}$ ✓ — identical, confirming CPI $=1$ makes the equation collapse to "one cycle each." The degenerate case behaves exactly as the picture predicts.

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Example 6 — Cell F: pathological inputs (zero, and a stall blow-up)

Step 1 — (a) The zero case. $T=0\times \text{CPI}\times T_c=0.$ Why this step? $N=0$ kills the whole product regardless of the other factors — no instructions, no time. It's the trivial floor, and it confirms $N$ is a genuine multiplicative factor (a sum-based formula would misbehave here).

Step 2 — (b) Build the effective CPI from a weighted average. Non-load instructions cost 1 cycle; loads cost $1+100=101$ cycles. Half and half: ${\text{CPI}}_{\text{eff}}=0.5\times 1+0.5\times 101=0.5+50.5=\mathrm{51.0.}$ Why this step? CPI is an average over the instruction mix, so when instruction classes cost different amounts we must weight each class by how often it occurs — here 50% cheap ($1$ cycle) and 50% expensive ($101$ cycles). A plain average of the two costs only works because the split happens to be 50/50; in general you weight by each class's frequency. This is the honest real CPI, not the ideal.

Step 3 — Total time with the blown-up CPI. $T=1.0\times 10^6\times 51.0\times 0.5\text{ ns}=25.5\times 10^6\text{ ns}=25.5\text{ ms}$ Why this step? We feed the effective CPI (not the fantasy CPI of 1) into the master equation, because that is the CPI the hardware actually experiences. Convert with the $10^6$ rule: $25.5\times 10^6\text{ ns}=25.5\text{ ms}$.

Recall Verify

(a) $0$ ms ✓. (b) A CPI of $51$ is worse than most CISC — proof that RISC's low-CPI promise is conditional on the memory system keeping up. When it doesn't, RISC's "1 cycle each" fantasy collapses. This is exactly why real chips spend transistors on caches, not just on the ISA.

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Example 7 — Cell G: real-world word problem

Step 1 — Recover CISC's instruction count $N$ from its known time. From $T=N\cdot \text{CPI}\cdot T_c$, solve for $N$: $N=\frac{T}{\text{CPI}\cdot T_c}$. $T_{c,\text{CISC}}=\frac{1}{2.0\times 10^9}=0.5\text{ ns},N_{\text{CISC}}=\frac{12\text{ s}}{4.5\times 0.5\times 10^{-9}\text{ s}}=5.333\times 10^9.$ Why this step? We aren't told $N$ directly, but the word problem gives us the time, so we invert the equation to extract the hidden instruction count. This is the bridge from English to arithmetic.

Step 2 — Scale to RISC's instruction count. $N_{\text{RISC}}=1.3\times 5.333\times 10^9=6.933\times 10^9.$ Why this step? "1.3× as many instructions" is a direct multiplier on $N$ — the compiler's expansion factor. We must convert the CISC instruction count into the RISC one before computing RISC's time, because the two machines run different amounts of work. See Compiler Optimization.

Step 3 — RISC cycle time and total time. $T_{c,\text{RISC}}=\frac{1}{1.8\times 10^9}=0.5556\text{ ns},$ $T_{\text{RISC}}=6.933\times 10^9\times 1.5\times 0.5556\times 10^{-9}\text{ s}\approx 5.78\text{ s}.$ Why this step? We flip RISC's frequency to a cycle time (same reciprocal rule as Example 4), then apply the master equation with RISC's own $N$, CPI and $T_c$. We keep everything in seconds here because the laptop's baseline is already in seconds — matching units means no conversion at the end.

Recall Verify

$\approx 5.78\text{ s}$ vs $12\text{ s}$ → the phone finishes in under half the laptop's time. Sanity: the CPI dropped $3\times$ ($4.5\to 1.5$), which alone would beat the $1.3\times$ instruction growth and the $1.11\times$ slower clock. Gut confirmed.

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Example 8 — Cell H: exam twist, solve for the unknown

Step 1 — Invert the equation for CPI. $\text{CPI}=\frac{T}{N\times T_c}.$ Why this step? The unknown is now CPI, and we're given the target time — so we rearrange the master equation to isolate CPI rather than multiplying forward. Same equation, different unknown solved for.

Step 2 — Plug in. $\text{CPI}=\frac{4.0\times 10^{-3}\text{ s}}{2.0\times 10^6\times 0.5\times 10^{-9}\text{ s}}=\frac{4.0\times 10^{-3}}{1.0\times 10^{-3}}=\mathrm{4.0.}$ Why this step? The denominator $N\cdot T_c=2.0\times 10^6\times 0.5\times 10^{-9}\text{ s}=1.0\times 10^{-3}\text{ s}$ is "time if CPI were 1." Dividing the target by it gives, in one shot, how much CPI headroom we have. Note the seconds cancel top-and-bottom, correctly leaving CPI dimensionless.

Recall Verify

$\text{CPI}=4.0$ is a huge budget — the RISC chip could stall an average of 4 cycles per instruction and still tie. So this RISC design has enormous slack; with realistic CPI $\approx 1.2$ it would demolish the CISC baseline. Reverse-check: $2.0\times 10^6\times 4.0\times 0.5\text{ ns}=4.0\text{ ms}$ ✓.

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Example 9 — Cell I: counting instructions from actual code (μop expansion)

Step 1 — Count instructions. CISC: one ADD [A],[B] per task → $N_{\text{CISC}}=200,000\times 1=200,000$. RISC: LOAD, LOAD, ADD, STORE = 4 per task → $N_{\text{RISC}}=200,000\times 4=800,000$. Why this step? $N$ is a literal count of executed instructions, so we must first read the code and count. RISC's load/store rule forbids memory operands in ADD, so it must spend 4 lines where CISC spends 1 — see Addressing Modes.

Step 2 — CISC time. $T_{\text{CISC}}=200,000\times 8\times 1.0\text{ ns}=1.6\times 10^6\text{ ns}=1.6\text{ ms}$ Why this step? Master equation on CISC. Its one instruction is expensive (8 cycles) because internally its microcode hides two loads and a store. Convert: $1.6\times 10^6\text{ ns}=1.6\text{ ms}$.

Step 3 — RISC time. $T_{\text{RISC}}=800,000\times 1.0\times 0.6\text{ ns}=0.48\times 10^6\text{ ns}=0.48\text{ ms}$ Why this step? Master equation on RISC, using the counted $N=800,000$. Each of its four instructions is cheap (1 cycle, short $T_c$). Convert: $0.48\times 10^6\text{ ns}=0.48\text{ ms}$.

Step 4 — Ratio (slower on top). $\frac{T_{\text{CISC}}}{T_{\text{RISC}}}=\frac{1.6}{0.48}\approx 3.33$ Why this step? CISC is slower, so its time goes on top; $3.33>1$ reads "RISC is 3.33× faster." The shared ms unit cancels, leaving a clean factor.

The bars show it visually: RISC's tower is 4 bricks tall (more instructions) but each brick is short and fast, while CISC is one brick, 8× as costly per cycle. The short-brick tower still ends up shorter.

Recall Verify

RISC $\approx 3.33\times$ faster even at 4× the instruction count, because the CISC ADD — hiding two memory loads and a store inside microcode — cost 8 cycles. This is Example 1's story told at the level of actual assembly, closing cell I of the matrix.

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Wrapping up the matrix

Every cell A–I now has a worked example: RISC wins (1), CISC wins (2), a tie (3), unit-flipping from frequency (4), the CPI $=1$ limit (5), zero and stall-blown inputs (6), a word problem (7), solving-for-the-unknown (8), and counting instructions from real μop expansion (9). The single thread through all of them: never judge by one factor — always form the product, watch the units, and compare with a ratio.

Recall Self-test

Given only $T=4.0\text{ ms}$, $N=2.0\text{M}$, $T_c=0.5\text{ ns}$, find CPI. ::: $\text{CPI}=T/(N\cdot T_c)=4.0\text{ms}/1.0\text{ms}=4.0$ (Example 8). A chip at $2.5$ GHz — what is $T_c$? ::: $T_c=1/(2.5\times 10^9)=0.4$ ns (Example 4). Half the instructions stall 100 cycles, rest cost 1 — effective CPI? ::: $0.5(1)+0.5(101)=51$ (Example 6).