CISC vs RISC philosophies: Exercises — Hardware deep dive

Level 1 — Recognition

Can you name the thing when you see it?

Recall Solution L1.1

x86 → CISC (variable length, memory operands in arithmetic)
ARMv8-A → RISC (fixed 32-bit, load/store)
VAX → CISC (famously rich instructions, microcode-heavy)
RISC-V → RISC (the name says it; fixed length, load/store)
Motorola 68k → CISC Why: the defining test is not speed or age — it is encoding + memory model. Fixed-length + load/store ⇒ RISC. See Instruction Encoding.

Recall Solution L1.2

False. RISC uses a load/store architecture: only LOAD/STORE may touch memory. You must first LOAD R2, [B] then ADD R3, R1, R2. See Addressing Modes.

Recall Solution L1.3

Fixed-length (e.g. 32-bit); x86 ranges from 1 to 15 bytes.

Level 2 — Application

Plug into the equation and turn the crank.

Recall Solution L2.1

WHAT we do: apply $CPU Time = N \times CPI \times T_{c}$ to each row. $CISC = 1.0 M \times 4.0 \times 1.25 ns = 5.0 ms$ $RISC = 1.5 M \times 1.1 \times 1.0 ns = 1.65 ms$ RISC wins, by a factor $5.0/1.65 \approx 3.03 \times$ . WHY: RISC used $50%$ more instructions, yet both $CPI$ and $T_{c}$ shrank enough to dominate. That is the entire RISC bet in one calculation.

Recall Solution L2.2

RISC:

LOAD  R1, [A]
LOAD  R2, [B]
ADD   R3, R1, R2
STORE [A], R3

CISC: ADD [A], [B] Memory accesses: RISC = 3 (2 loads + 1 store), CISC = 3 internally too (read A, read B, write A). Same memory traffic — the difference is where it is expressed: RISC exposes it as instructions, CISC hides it inside microcode. See Microcode and Micro-operations.

Recall Solution L2.3

$RISC = 2 M \times 1.2 \times 0.5 ns = 1.2 ms$ $CISC = 1.2 M \times 5 \times 0.8 ns = 4.8 ms$ RISC is $4.8/1.2 = 4 \times$ faster.

Level 3 — Analysis

Take it apart: which factor is doing the work?

Recall Solution L3.1

Halve CPI: $1.0 M \times 2.0 \times 1.25 ns = 2.5 ms$
Halve $T_{c}$ : $1.0 M \times 4.0 \times 0.625 ns = 2.5 ms$ They tie at 2.5 ms. Because the equation is a product, halving any single factor halves the total. This is why RISC attacks both CPI and $T_{c}$ — the gains multiply. See Pipelining.

Recall Solution L3.2

No — the ISA is still CISC. Two layers:

Architecture (ISA): what the programmer/compiler sees — variable length, memory operands ⇒ CISC. Unchanged.
Microarchitecture: how silicon executes it — a decoder splits each instruction into RISC-like micro-ops running on a fast core. So modern x86 is CISC ISA, RISC-style microarchitecture — a hybrid. See x86 vs ARM and Microcode and Micro-operations.

Recall Solution L3.3

Follow the cyan boxes (RISC): each is the same width, so the fetch unit knows exactly where the next instruction begins — it can start decoding instruction $i + 1$ while $i$ executes. That regular overlap is a pipeline. Follow the amber box (CISC): its length is unknown until partly decoded (1–15 bytes), so the fetch stage must wait to find the boundary — the red stall bar. Variable length ⇒ the pipeline can't confidently prefetch, raising effective $CPI$ . This is the mechanical reason fixed-length encoding pipelines better. See Instruction Encoding.

Level 4 — Synthesis

Combine ideas to build or justify a design.

Recall Solution L4.1

Lean CISC-ish / dense encoding. Reasoning:

Code size (bytes of flash) $\approx N \times$ avg-instruction-size. Scarce flash ⇒ minimise this. CISC's variable, compact encoding wins here.
No pipeline ⇒ RISC's biggest advantage (clean overlap lowering CPI) is unavailable, so RISC loses its main lever.
$T_{c}$ matters little at low clock speeds; energy per instruction and code density dominate. Real answer: this is exactly why ARM Thumb / RISC-V compressed (C) extensions exist — a RISC core with a compressed 16-bit encoding to reclaim code density. So: RISC execution model + dense encoding = best blend. See Compiler Optimization.

Recall Solution L4.2

WHAT: set RISC time $=$ CISC time and solve for the instruction ratio. $N_{R} \cdot 1.1 \cdot 1.0 = N_{C} \cdot 4.0 \cdot 1.25$ $\frac{N _{R}}{N _{C}} = \frac{4.0 \times 1.25}{1.1 \times 1.0} = \frac{5.0}{1.1} \approx 4.55$ Interpretation: RISC could execute up to $\approx 4.55 \times$ as many instructions as CISC and still tie. In L2.1 the real ratio was only $1.5 \times$ — far below break-even — so RISC won comfortably. This quantifies how much slack the RISC bet has.

Level 5 — Mastery

Full multi-step reasoning; defend every number.

Recall Solution L5.1

(a) $1.6 M \times 1.1 \times 1.0 ns = 1.76 ms$ . (b) CISC time $= 1.0 M \times 4.0 \times 1.25 ns = 5.0 ms$ . Speedup $= 5.0/1.76 \approx 2.84 \times$ . (c) The compiler attacked $N$ (fewer instructions) — the one factor software controls. This is the core RISC philosophy: hardware stays simple and fast ( $CPI, T_{c}$ ), while the compiler carries the complexity of producing tight code. The improvement came for free from software, not silicon.

Recall Solution L5.2

CISC-favouring workload: memory-bandwidth-starved code fetched over a slow bus (e.g. old machines, some embedded flash). Dense variable-length encoding ⇒ fewer bytes fetched per operation ⇒ less time lost to instruction fetch. Here fetch bandwidth, not $CPI$ , is the bottleneck. What flips it back to RISC: add a pipeline + instruction cache. Once instructions are cached, fetch bandwidth stops being the bottleneck, and RISC's clean overlap (low CPI) + short $T_{c}$ dominate again. This is precisely the historical transition of the 1980s. See Pipelining.

Recall One-figure summary: the ladder you just climbed