Before you can weigh those two bets, you need to know exactly what an "instruction" is, what a "register" is, what a "cycle" is, and — once those words exist — how a small three-factor timing formula is built. This page assumes nothing. We build every word and every symbol from the ground up, then assemble the formula.
Figure s01 (below): a CPU box on the left holding three little register boxes, joined to its registers by a short orange arrow labelled "short = fast", and joined to a large memory box on the right by a long arrow labelled "long trip = slow". The picture makes one point: registers are near, memory is far.
Figure s01 — Registers sit inside the CPU (near, fast); memory sits far away (slow to reach). This distance is why RISC does arithmetic only in registers.
Before either symbol appears again, pin down the two words themselves.
Both words are fully unpacked in the parent CISC vs RISC philosophies. For now just hold this contrast: CISC = few heavy orders; RISC = many light orders. Every symbol below is what we need to measure which bet wins.
Figure s02 (below): a teal square-wave "clock signal" rising and falling; one full rise-and-fall is bracketed by an orange arrow labelled "Tc seconds", and dotted plum lines mark each "tick". It shows a cycle as the gap between two ticks.
Figure s02 — The clock alternates low/high; one full period is one cycle, lasting Tc seconds. Each dotted line is a tick.
Why does the CISC/RISC debate care about Tc? Because simpler hardware can tick faster — a shorter, cleaner path between switches means the drummer can beat quicker. RISC keeps hardware simple partly to shrink Tc.
Not every instruction finishes in one tick. A simple "add two registers" might take one cycle; a heavy "read memory, multiply, write memory" might take several. We need a symbol for how many ticks an instruction costs.
Figure s03 (below): a bar chart of "cycles this instruction costs" for four instructions — a register-only ADD (1 cycle), a LOAD (3), a heavy MUL (4), and a memory-to-memory CISC ADD (5) — with a dashed orange line at 1 marking the "RISC dream: CPI → 1". Taller bar = more cycles eaten.
Figure s03 — Different instructions cost different numbers of cycles; CPI is their program-weighted average. Light RISC ops sit near 1; heavy CISC ops rise well above it.
The diagram below is read top-to-bottom: each arrow means "this is needed to understand that." Start at the roots and follow the arrows down into the final "CISC vs RISC bet" node.
CPU registers and memory (s01) let us define an Instruction.
An instruction is the unit we count, giving N (the instruction count).
The clock and cycle (s02) give us Tc (cycle time) and, together with the instruction, CPI (cycles per instruction).
N, CPI, and Tc combine into the CPU Time equation (Section 5).
That equation, plus the three structural rules (load/store, fixed vs variable encoding, microcode) and pipelining, is everything the parent topic needs to argue which design wins.
