CISC vs RISC philosophies: Foundations — Hinglish deep dive

5.1.1 · D1 · Hardware › Instruction Set Architecture (ISA) › CISC vs RISC philosophies

In dono bets ko weigh karne se pehle, tumhe exactly jaanna hoga ki ek "instruction" kya hota hai, ek "register" kya hota hai, ek "cycle" kya hota hai, aur — jab yeh words exist ho jayein — ek chhoti-si teen-factor timing formula kaise banti hai. Is page mein kuch bhi assume nahi kiya gaya. Hum har word aur har symbol scratch se banate hain, phir formula assemble karte hain.

0. Woh machine jis ki hum baat kar rahe hain

Figure s01 (neeche): left mein ek CPU box jisme teen chhote register boxes hain, jo apne registers se ek chhote orange arrow se juda hai jis par likha hai "short = fast", aur right mein ek bade memory box se ek lambe arrow se juda hai jis par likha hai "long trip = slow". Yeh picture ek hi baat karti hai: registers paas hain, memory door hai.

Figure s01 — Registers CPU ke andar hote hain (paas, fast); memory door hoti hai (reach karna slow). Yahi distance ki wajah se RISC sirf registers mein arithmetic karta hai.

1. "CISC" aur "RISC" asal mein kya naam hain

Koi bhi symbol dobara aane se pehle, dono words khud pin down karo.

Dono words parent CISC vs RISC philosophies mein fully unpack hain. Abhi bas yeh contrast pakad lo: CISC = kam bhaari orders; RISC = zyada halki orders. Neeche har symbol wahi hai jo hume measure karne ke liye chahiye ki kaun sa bet jeetta hai.

2. Instruction — program ka atom

Ek program simply instructions ki ek list hai, jo top se bottom tak chalti hai (occasional jumps ke saath).

3. Clock aur cycle

Figure s02 (neeche): ek teal square-wave "clock signal" jo rise aur fall karti hai; ek full rise-and-fall ko ek orange arrow ne bracket kiya hai jis par " $T_{c}$ seconds" likha hai, aur dotted plum lines har "tick" ko mark karti hain. Yeh cycle ko do ticks ke beech ke gap ke roop mein dikhata hai.

Figure s02 — Clock low/high alternate karta hai; ek full period ek cycle hai, jo $T_{c}$ seconds tak chalta hai. Har dotted line ek tick hai.

CISC/RISC debate $T_{c}$ ki kyon parwah karta hai? Kyunki simpler hardware faster tick kar sakta hai — switches ke beech ek shorter, cleaner path ka matlab hai drummer tezi se beat kar sakta hai. RISC hardware ko simple isliye bhi rakhta hai taaki $T_{c}$ chhota ho sake.

4. Cycles per instruction — symbol CPI

Har instruction ek tick mein nahi khatam hoti. Ek simple "do registers add karo" shayad ek cycle le; ek bhaari "memory read karo, multiply karo, memory write karo" kai le sakta hai. Hume ek symbol chahiye ek instruction kitne ticks cost karti hai ke liye.

Figure s03 (neeche): "cycles this instruction costs" ka ek bar chart chaar instructions ke liye — ek register-only ADD (1 cycle), ek LOAD (3), ek bhaari MUL (4), aur ek memory-to-memory CISC ADD (5) — ek dashed orange line ke saath 1 par jo "RISC dream: CPI → 1" mark karta hai. Uncha bar = zyada cycles khaye.

Figure s03 — Alag instructions alag number of cycles cost karti hain; CPI unka program-weighted average hai. Halki RISC ops 1 ke paas rehti hain; bhaari CISC ops usse kaafi upar jaati hain.

Common mistake CPI ISA ki fixed property nahi hai — memory stalls use inflate karte hain

Galat idea: "Ek RISC add ka CPI hamesha 1 hota hai, isliye RISC ka CPI 1 hai." Fix: ek real machine mein average CPI stalls ki wajah se upar khicha jaata hai — woh cycles jinhein CPU wait karte hue waste karta hai. Sabse bada cause hai cache/memory hierarchy: registers instant hain, ek chhhota fast cache kuch cycles ka hai, lekin ek cache miss jo main memory tak pahunchna pade woh tens ya hundreds of cycles cost kar sakta hai. Ek single LOAD jo miss ho jaye dozens of perfect register ops se average CPI mein zyada add kar sakta hai. Isliye measured CPI program ke memory behaviour par depend karta hai, sirf ISA par nahi — aur yahi exact wajah hai ki real RISC CPI (say) 1.1 hota hai, clean 1.0 nahi.

5. Timing equation assemble karna

Ab har symbol earn ho gaya hai, isliye hum woh formula build kar sakte hain jo parent note use karta hai.

6. Do structural words jo tumhe zaroori jaanne chahiye

7. Foundations topic ko kaise feed karti hain

Neeche ka diagram top-to-bottom padha jaata hai: har arrow ka matlab hai "yeh samajhne ke liye woh zaroori hai." Roots se shuru karo aur arrows follow karte hue final "CISC vs RISC bet" node tak pahuncho.

CPU registers aur memory (s01) hume ek Instruction define karne dete hain.
Ek instruction woh unit hai jise hum count karte hain, $N$ (instruction count) deta hai.
Clock aur cycle (s02) hume $T_{c}$ (cycle time) deta hai aur, instruction ke saath mila ke, CPI (cycles per instruction).
$N$ , CPI, aur $T_{c}$ milkar CPU Time equation (Section 5) banaate hain.
Woh equation, plus teen structural rules (load/store, fixed vs variable encoding, microcode) aur pipelining, yeh sab kuch hai jo parent topic ko argue karne ke liye chahiye ki kaun sa design jeetta hai.

Wapas upar jaao: CISC vs RISC philosophies.

Teen knobs ka apna detailed treatment hai CPU Performance Equation mein.
RISC kyun arithmetic registers mein rakhta hai yeh Addressing Modes aur Compiler Optimization se connect karta hai.
Har side implement karne wale real chips: x86 vs ARM.

Equipment checklist

Kya tumhe pehle se pata hai…

"CISC" aur "RISC" highest level par kya naam hain?

CISC = kam, bhaari, variable-length instructions (complexity hardware mein); RISC = zyada, simple, fixed-length instructions (complexity compiler mein).

CPU ke andar ek tiny fast box; ise reach karna near-instant hai, jabki memory reach karne ka matlab hai chip ke bahar ek lamba, slow trip.

Symbol

N

kya count karta hai?

Actually execute hue instructions ki total number (loops har pass count kiye), type ki gayi lines nahi.

Ek clock cycle kya hai?

CPU ke internal drummer ka ek tick; har switch sirf ek tick par update ho sakta hai.

T_{c}

ka kya matlab hai aur uski units kya hain?

Seconds per cycle — do ticks ke beech ka gap; yeh clock speed ka reciprocal hai.

CPI

ka kya matlab hai, aur ise 1 se upar kya push karta hai?

Average clock cycles per instruction; memory/cache stalls (especially cache misses) average ko real machines mein upar khichte hain.

CPU Time equation kaise build ki jaati hai?

N

instructions × CPI cycles each ×

T_{c}

seconds each

=

total seconds:

CPU Time = N \times CPI \times T_{c}

Example mein "relative

T_{c}

" ka kya matlab hai?

Faster design ke cycle time ko baseline

1.0

liya jaata hai; doosre design ka

1.25

matlab uska cycle 25% longer hai — sirf results ka ratio matter karta hai.

Load/store rule kya hai?

Sirf LOAD aur STORE memory ko touch karte hain; saari arithmetic register-to-register hoti hai (RISC ki defining trait).

Fixed vs variable-length encoding kya hoti hai?

Fixed = har instruction same size (RISC, fetch/pipeline karna easy); variable = alag-alag sizes (CISC, compact lekin aage decode karna mushkil).

Microcode kya karta hai?

Ek complex CISC instruction ko kai tiny internal micro-ops mein expand karta hai jo silicon run karta hai.