CISC vs RISC philosophies: Exercises — Hinglish deep dive

5.1.1 · D4 · Hardware › Instruction Set Architecture (ISA) › CISC vs RISC philosophies

Level 1 — Recognition

Kya tum cheez ko dekh ke naam de sakte ho?

Recall Solution L1.1

x86 → CISC (variable length, arithmetic mein memory operands)
ARMv8-A → RISC (fixed 32-bit, load/store)
VAX → CISC (mashoor rich instructions, microcode-heavy)
RISC-V → RISC (naam hi bata deta hai; fixed length, load/store)
Motorola 68k → CISC Kyun: defining test speed ya age nahi hai — woh hai encoding + memory model. Fixed-length + load/store ⇒ RISC. Dekho Instruction Encoding.

Recall Solution L1.2

False. RISC ek load/store architecture use karta hai: sirf LOAD/STORE hi memory touch kar sakte hain. Tumhe pehle LOAD R2, [B] karna hoga, phir ADD R3, R1, R2. Dekho Addressing Modes.

Recall Solution L1.3

Fixed-length (jaise 32-bit); x86 ki range 1 se 15 bytes tak hai.

Level 2 — Application

Equation mein plug karo aur crank ghumaao.

Recall Solution L2.1

Kya karenge: har row par $CPU Time = N \times CPI \times T_{c}$ apply karenge. $CISC = 1.0 M \times 4.0 \times 1.25 ns = 5.0 ms$ $RISC = 1.5 M \times 1.1 \times 1.0 ns = 1.65 ms$ RISC jeetta hai, $5.0/1.65 \approx 3.03 \times$ ke factor se. Kyun: RISC ne $50%$ zyada instructions use kiye, phir bhi $CPI$ aur $T_{c}$ dono itna shrink hue ki dominate kar gaye. Yahi ek calculation mein poora RISC bet hai.

Recall Solution L2.2

RISC:

LOAD  R1, [A]
LOAD  R2, [B]
ADD   R3, R1, R2
STORE [A], R3

CISC: ADD [A], [B] Memory accesses: RISC = 3 (2 loads + 1 store), CISC = internally bhi 3 (read A, read B, write A). Same memory traffic — fark sirf yahan hai ki kahan express hota hai: RISC isse instructions ki tarah expose karta hai, CISC isse microcode ke andar chupa leta hai. Dekho Microcode and Micro-operations.

Recall Solution L2.3

$RISC = 2 M \times 1.2 \times 0.5 ns = 1.2 ms$ $CISC = 1.2 M \times 5 \times 0.8 ns = 4.8 ms$ RISC $4.8/1.2 = 4 \times$ faster hai.

Level 3 — Analysis

Ise tukdon mein tod: kaun sa factor kaam kar raha hai?

Recall Solution L3.1

CPI half karo: $1.0 M \times 2.0 \times 1.25 ns = 2.5 ms$
$T_{c}$ half karo: $1.0 M \times 4.0 \times 0.625 ns = 2.5 ms$ Dono 2.5 ms par tie karte hain. Kyunki equation ek product hai, kisi bhi ek factor ko half karne se total half ho jaata hai. Isliye RISC dono CPI aur $T_{c}$ par attack karta hai — gains multiply hote hain. Dekho Pipelining.

Recall Solution L3.2

Nahi — ISA abhi bhi CISC hai. Do layers:

Architecture (ISA): programmer/compiler kya dekhta hai — variable length, memory operands ⇒ CISC. Unchanged.
Microarchitecture: silicon ise kaise execute karta hai — ek decoder har instruction ko RISC-jaisi micro-ops mein split karta hai jo ek fast core par chalti hain. Toh modern x86 CISC ISA, RISC-style microarchitecture hai — ek hybrid. Dekho x86 vs ARM aur Microcode and Micro-operations.

Recall Solution L3.3

Cyan boxes (RISC) follow karo: har ek same width ki hai, toh fetch unit ko exactly pata hai agli instruction kahan shuru hoti hai — woh instruction $i + 1$ ko decode karna shuru kar sakta hai jabki $i$ execute ho raha hota hai. Woh regular overlap ek pipeline hai. Amber box (CISC) follow karo: iski length partially decode hone tak unknown hoti hai (1–15 bytes), toh fetch stage ko boundary find karne ke liye wait karna padta hai — red stall bar. Variable length ⇒ pipeline confidently prefetch nahi kar sakta, effective $CPI$ badhta hai. Yahi mechanical reason hai ki fixed-length encoding better pipeline hoti hai. Dekho Instruction Encoding.

Level 4 — Synthesis

Ideas ko combine karke ek design build ya justify karo.

Recall Solution L4.1

Lean CISC-ish / dense encoding. Reasoning:

Code size (flash ke bytes) $\approx N \times$ avg-instruction-size. Scarce flash ⇒ ise minimize karo. CISC ka variable, compact encoding yahan jeetta hai.
No pipeline ⇒ RISC ka sabse bada advantage (clean overlap jo CPI kam karta hai) unavailable hai, toh RISC apna main lever khota hai.
$T_{c}$ low clock speeds par kam matter karta hai; energy per instruction aur code density dominate karti hai. Real answer: yahi reason hai kyun ARM Thumb / RISC-V compressed (C) extensions exist karte hain — ek RISC core with ek compressed 16-bit encoding jo code density wapas reclaim karta hai. Toh: RISC execution model + dense encoding = best blend. Dekho Compiler Optimization.

Recall Solution L4.2

Kya karein: RISC time $=$ CISC time set karo aur instruction ratio ke liye solve karo. $N_{R} \cdot 1.1 \cdot 1.0 = N_{C} \cdot 4.0 \cdot 1.25$ $\frac{N _{R}}{N _{C}} = \frac{4.0 \times 1.25}{1.1 \times 1.0} = \frac{5.0}{1.1} \approx 4.55$ Interpretation: RISC CISC se $\approx 4.55 \times$ tak zyada instructions execute kar sakta hai aur phir bhi tie kar sakta hai. L2.1 mein real ratio sirf $1.5 \times$ tha — break-even se bahut neechhe — isliye RISC aaram se jeeta. Yeh quantify karta hai ki RISC bet mein kitna slack hai.

Level 5 — Mastery

Poora multi-step reasoning; har number defend karo.

Recall Solution L5.1

(a) $1.6 M \times 1.1 \times 1.0 ns = 1.76 ms$ . (b) CISC time $= 1.0 M \times 4.0 \times 1.25 ns = 5.0 ms$ . Speedup $= 5.0/1.76 \approx 2.84 \times$ . (c) Compiler ne $N$ par attack kiya (kam instructions) — woh ek factor jise software control kar sakta hai. Yahi RISC philosophy ki core hai: hardware simple aur fast rehta hai ( $CPI, T_{c}$ ), jabki compiler tight code produce karne ki complexity uthata hai. Improvement software se free mein aayi, silicon se nahi.

Recall Solution L5.2

CISC-favouring workload: memory-bandwidth-starved code jo slow bus par fetch ho raha ho (jaise old machines, kuch embedded flash). Dense variable-length encoding ⇒ per operation fewer bytes fetch ⇒ instruction fetch mein kam time waste. Yahan fetch bandwidth bottleneck hai, $CPI$ nahi. Kya ise RISC ki taraf wapas flip karta hai: ek pipeline + instruction cache add karo. Jab instructions cache ho jaayein, fetch bandwidth bottleneck rehti nahi, aur RISC ka clean overlap (low CPI) + short $T_{c}$ dobara dominate karta hai. Yahi 1980s ka historical transition tha. Dekho Pipelining.

Recall Ek figure summary: woh ladder jo tumne abhi chadi