Worked examples — CISC vs RISC philosophies

5.1.1 · D3 · Hardware › Instruction Set Architecture (ISA) › CISC vs RISC philosophies

Yeh page CISC vs RISC philosophies ki hands-on companion hai. Wahan humne philosophy build ki thi; yahan hum compute karte hain. Har example neeche diye matrix ka ek cell cover karta hai, taaki end tak koi bhi CISC-vs-RISC arithmetic question exam mein aisa na ho jo tumne already worked form mein na dekha ho.

Koi bhi number chhune se pehle, chalte hain us ek tool ko re-anchor karte hain jis par sab kuch tika hua hai.

Hum ise baar baar use karenge, toh chalte hain ek baar ise picture karte hain.

Figure ko ek volume ki tarah padho: $N$ depth hai, $\text{CPI}$ width hai, $T_c$ height hai, aur CPU time woh box hai jo ye sab enclose karte hain. Ek edge badhao aur do ghataao, aur box phir bhi shrink ho sakta hai — isliye RISC afford kar sakta hai $N$ badhana agar woh CPI aur $T_c$ zyada hard shrink kare. Har box ke neeche number uska volume = CPU time hai.

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The scenario matrix

Har CISC-vs-RISC computation jo tumse kabhi bhi poochi jaayegi, woh in cells mein se ek mein hoti hai. Har row ek case class hai; last column us example ka naam deta hai jo ise cover karta hai.

#	Case class	Tricky kyon hai	Covered by
A	RISC wins (the "normal" bet pays off)	zyada $N$, lekin CPI + $T_c$ dominate karte hain	Example 1
B	CISC wins (the bet fails)	jab RISC ka $N$ blow-up bahut bada ho	Example 2
C	Exact tie	boundary — koi bhi faster nahi	Example 3
D	Mixed units ($T_c$ vs frequency $f$)	GHz diya hai, ns nahi	Example 4
E	Degenerate: $\text{CPI}=1$ everywhere	limiting "ideal RISC"	Example 5
F	Zero / pathological input	$N=0$, ya stall se CPI blow up ho jaaye	Example 6
G	Real-world word problem	English → equation mein translate karo	Example 7
H	Exam twist: solve for the unknown	answer diya hai, ek factor dhundho	Example 8
I	Instruction-count from code (μop expansion)	RISC lines vs ek CISC line count karo	Example 9

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Example 1 — Cell A: the RISC bet pays off

Step 1 — CISC time compute karo. $T_{\text{CISC}}=1.0\times 10^6\times 4.0\times 1.25\text{ ns}=5.0\times 10^6\text{ ns}=5.0\text{ ms}$ Yeh step kyun? Hum sirf wahi ek equation apply kar rahe hain — koi shortcuts nahi. Hum end mein milliseconds mein convert karte hain taaki dono numbers ek nazar mein comparable hon ($1\text{ ms}=10^6\text{ ns}$, toh decimal 6 jagah move karo).

Step 2 — RISC time compute karo. $T_{\text{RISC}}=1.5\times 10^6\times 1.1\times 1.0\text{ ns}=1.65\times 10^6\text{ ns}=1.65\text{ ms}$ Yeh step kyun? Same equation, RISC ke numbers ke saath. Dhyaan do bada pehla factor lekin chhote baaki do. Phir wahi $10^6$ conversion se $1.65\times 10^6\text{ ns}=1.65\text{ ms}$.

Step 3 — Ratio lo (slower upar). $\frac{T_{\text{CISC}}}{T_{\text{RISC}}}=\frac{5.0}{1.65}\approx 3.03$ Yeh step kyun? "Kitne factor se" ka jawab ratio se milta hai, difference se nahi — yeh batata hai kitne times faster, units se independent. CISC (slower, bigger time) ko upar rakha taaki answer padhe "RISC is 3.03× faster."

Recall Verify

Units: $\text{count}\times \text{(cycles/instr)}\times \text{(ns/cycle)}=\text{ns}$ ✓. RISC $\approx 3\times$ faster hai despite 50% zyada instructions — extra $N$ crush ho gaya $3.6\times$ CPI drop aur $1.25\times$ cycle-time drop se. Yahi puri RISC argument ek ratio mein hai.

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Example 2 — Cell B: the bet fails, CISC wins

Step 1 — CISC time. $T_{\text{CISC}}=0.5\times 10^6\times 6.0\times 1.0\text{ ns}=3.0\times 10^6\text{ ns}=3.0\text{ ms}$ Yeh step kyun? Same equation. CISC ka high CPI uski weakness hai — lekin uska tiny $N$ dekho. Convert: $3.0\times 10^6\text{ ns}=3.0\text{ ms}$.

Step 2 — RISC time. $T_{\text{RISC}}=6.0\times 10^6\times 1.0\times 0.9\text{ ns}=5.4\times 10^6\text{ ns}=5.4\text{ ms}$ Yeh step kyun? RISC ka $N$ 12× explode hua kyunki ek CISC string instruction ko poore software loop ki zaroorat thi. Yeh uske CPI/$T_c$ advantage se zyada hai. Convert: $5.4\times 10^6\text{ ns}=5.4\text{ ms}$.

Step 3 — Ratio (slower upar). $\frac{T_{\text{RISC}}}{T_{\text{CISC}}}=\frac{5.4}{3.0}=1.8$ Yeh step kyun? Yahan RISC slower hai, toh RISC ka time upar jaata hai; result $1.8$ padhta hai "RISC is 1.8× slower than CISC." Hamesha bada time upar rakho taaki factor $>1$ ho.

Recall Verify

RISC 1.8× slower hai yahan. Lesson yeh hai: RISC ka bet ek bet hai, koi law nahi. Jab ek workload exactly us specialised instruction par map karta hai jo CISC provide karta hai (string moves, REP MOVSB on x86), tab $N$ blow-up sab kuch overwhelm kar sakta hai. Isliye modern RISC ISAs ne richer extensions add kiye — dekho x86 vs ARM.

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Example 3 — Cell C: the exact tie

Step 1 — CISC time. $T_{\text{CISC}}=2.0\times 10^6\times 3.0\times 1.0\text{ ns}=6.0\times 10^6\text{ ns}=6.0\text{ ms}$ Yeh step kyun? Hum CISC se start karte hain kyunki hum hamesha pehle dono raw times compute karte hain, phir compare karte hain. $10^6$ rule se ms mein convert karo taaki dono ek hi scale par padhein: $6.0\times 10^6\text{ ns}=6.0\text{ ms}$.

Step 2 — RISC time. $T_{\text{RISC}}=3.0\times 10^6\times 2.0\times 1.0\text{ ns}=6.0\times 10^6\text{ ns}=6.0\text{ ms}$ Yeh step kyun? RISC ke liye same equation. Products same number par land karte hain — dono $6.0\text{ ms}$ dete hain usi $10^6$ conversion ke baad, jo is boundary case ka pura point hai.

Step 3 — Ratio (koi bhi upar). $\frac{T_{\text{CISC}}}{T_{\text{RISC}}}=\frac{6.0}{6.0}=1.00$ Yeh step kyun? Jab koi bhi slower nahi hota, ratio exactly $1$ hota hai chahe koi bhi time upar rakho — yeh tie ka unambiguous fingerprint hai.

Recall Verify

Ratio $=1.00$ → dead tie. Yeh boundary case hai: RISC ka $\times 1.5$ on $N$ exactly cancel karta hai uska $\times \frac{2}{3}$ on CPI ($1.5\times \frac{2}{3}=1$). Aise boundary cases prove karte hain ki equation ek genuine trade-off surface hai, ek one-sided win nahi.

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Example 4 — Cell D: cycle time nahi, frequency diya hai

Step 1 — Frequency ko cycle time mein convert karo. Clock frequency $f$ ticks per second count karta hai; cycle time sirf uska reciprocal hai, kyunki "seconds per tick" "ticks per second" ka ulta hai: $T_c=\frac{1}{f}.$ $T_{c,\text{CISC}}=\frac{1}{2.0\times 10^9\text{ Hz}}=0.5\text{ ns},T_{c,\text{RISC}}=\frac{1}{2.5\times 10^9\text{ Hz}}=0.4\text{ ns}.$ Yeh step kyun? Equation ko seconds per cycle chahiye; problem ne cycles per second diya hai. Pehle flip karna zaroori hai warna har unit downstream galat ho jaayega. Yeh exam ka sabse common trap hai.

Step 2 — CISC time. $T_{\text{CISC}}=1.0\times 10^6\times 5.0\times 0.5\text{ ns}=2.5\times 10^6\text{ ns}=2.5\text{ ms}$ Yeh step kyun? Ab $T_c$ nanoseconds mein hai, toh hum teen factors ko usual taur par multiply kar sakte hain. Result ko $10^6$ rule se convert karo: $2.5\times 10^6\text{ ns}=2.5\text{ ms}$.

Step 3 — RISC time. $T_{\text{RISC}}=1.4\times 10^6\times 1.2\times 0.4\text{ ns}=0.672\times 10^6\text{ ns}=0.672\text{ ms}$ Yeh step kyun? Same equation RISC ke converted $T_c$ ke saath. Hum dono machines ke liye same units (ns) rakhte hain taaki comparison apples-to-apples ho; phir convert karo: $0.672\times 10^6\text{ ns}=0.672\text{ ms}$.

Step 4 — Ratio (slower upar). $\frac{T_{\text{CISC}}}{T_{\text{RISC}}}=\frac{2.5}{0.672}\approx 3.72$ Yeh step kyun? CISC yahan slower machine hai, toh uska time upar jaata hai; $3.72>1$ directly padhta hai "RISC is 3.72× faster." Ratio shared ms unit bhi cancel karta hai, ek pure number deta hai.

Recall Verify

$\text{Hz}=1/\text{s}$, toh $1/\text{Hz}=\text{s}$ ✓ — reciprocal genuinely ek time produce karta hai. RISC $\approx 3.7\times$ faster hai. Agar tumne GHz flip karna bhool ke $2.0$ aur $2.5$ directly as times plug kiye hote, toh har answer $10^{18}$ ke factor se galat hota — units tumhari alarm bell hain.

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Example 5 — Cell E: the ideal-RISC limit, $\text{CPI}=1$

Step 1 — Cycle time. $T_c=\frac{1}{3.0\times 10^9}=0.\overline{3}\text{ ns}\approx 0.3333\text{ ns}$ Yeh step kyun? Frequency → time, same reciprocal pehle jaisa, kyunki equation seconds per cycle maangti hai.

Step 2 — Total time at the CPI floor. $T=3.0\times 10^6\times 1.0\times 0.3333\text{ ns}=1.0\times 10^6\text{ ns}=1.0\text{ ms}$ Yeh step kyun? $\text{CPI}=1$ ke saath, middle factor 1 se multiply karta hai aur effectively disappear ho jaata hai — time $N\times T_c$ par collapse ho jaata hai, yaani exactly ek tick per instruction. Hum ise explicitly compute karte hain taaki woh collapse dikhe, phir convert karo $1.0\times 10^6\text{ ns}=1.0\text{ ms}$. Yeh woh limiting best case hai jo ek single-issue pipeline reach kar sakti hai; CPI $=1$ se neeche nahi jaa sakte bina ek cycle mein ek se zyada instruction issue kiye (superscalar, out of scope yahan). Dekho Pipelining.

Recall Verify

$N\times T_c=3.0\times 10^6\times 0.3333\text{ ns}=1.0\text{ ms}$ ✓ — identical, confirm karta hai ki CPI $=1$ equation ko "ek cycle each" tak collapse kar deta hai. Degenerate case exactly waisa behave karta hai jaise picture predict karti hai.

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Example 6 — Cell F: pathological inputs (zero, aur ek stall blow-up)

Step 1 — (a) The zero case. $T=0\times \text{CPI}\times T_c=0.$ Yeh step kyun? $N=0$ poore product ko kill kar deta hai baaki factors chahe jo bhi hon — koi instructions nahi, koi time nahi. Yeh trivial floor hai, aur yeh confirm karta hai ki $N$ ek genuine multiplicative factor hai (ek sum-based formula yahan misbehave karta).

Step 2 — (b) Weighted average se effective CPI build karo. Non-load instructions cost 1 cycle; loads cost $1+100=101$ cycles. Half and half: ${\text{CPI}}_{\text{eff}}=0.5\times 1+0.5\times 101=0.5+50.5=\mathrm{51.0.}$ Yeh step kyun? CPI instruction mix par ek average hai, toh jab instruction classes alag amounts cost karti hain to hum har class ko weight karte hain uski frequency se — yahan 50% cheap ($1$ cycle) aur 50% expensive ($101$ cycles). Dono costs ka plain average tab hi kaam karta hai jab split 50/50 ho; generally tum har class ki frequency se weight karte ho. Yeh honest real CPI hai, ideal nahi.

Step 3 — Blown-up CPI ke saath total time. $T=1.0\times 10^6\times 51.0\times 0.5\text{ ns}=25.5\times 10^6\text{ ns}=25.5\text{ ms}$ Yeh step kyun? Hum effective CPI (fantasy CPI of 1 nahi) ko master equation mein feed karte hain, kyunki yahi woh CPI hai jo hardware actually experience karta hai. $10^6$ rule se convert karo: $25.5\times 10^6\text{ ns}=25.5\text{ ms}$.

Recall Verify

(a) $0$ ms ✓. (b) CPI of $51$ zyattar CISC se bhi worse hai — proof ki RISC ka low-CPI promise conditional hai memory system ke cooperate karne par. Jab nahi karta, RISC ka "1 cycle each" fantasy collapse ho jaata hai. Exactly isliye real chips transistors caches par spend karte hain, sirf ISA par nahi.

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Example 7 — Cell G: real-world word problem

Step 1 — CISC ka instruction count $N$ uske known time se recover karo. $T=N\cdot \text{CPI}\cdot T_c$ se, $N$ ke liye solve karo: $N=\frac{T}{\text{CPI}\cdot T_c}$. $T_{c,\text{CISC}}=\frac{1}{2.0\times 10^9}=0.5\text{ ns},N_{\text{CISC}}=\frac{12\text{ s}}{4.5\times 0.5\times 10^{-9}\text{ s}}=5.333\times 10^9.$ Yeh step kyun? $N$ directly nahi diya hai, lekin word problem ne time diya hai, toh hum equation ko invert karte hain hidden instruction count extract karne ke liye. Yeh bridge hai English se arithmetic tak.

Step 2 — RISC ke instruction count tak scale karo. $N_{\text{RISC}}=1.3\times 5.333\times 10^9=6.933\times 10^9.$ Yeh step kyun? "1.3× as many instructions" $N$ par ek direct multiplier hai — compiler ka expansion factor. RISC ka time compute karne se pehle CISC instruction count ko RISC wale mein convert karna zaroori hai, kyunki dono machines alag amount ka kaam run karti hain. Dekho Compiler Optimization.

Step 3 — RISC cycle time aur total time. $T_{c,\text{RISC}}=\frac{1}{1.8\times 10^9}=0.5556\text{ ns},$ $T_{\text{RISC}}=6.933\times 10^9\times 1.5\times 0.5556\times 10^{-9}\text{ s}\approx 5.78\text{ s}.$ Yeh step kyun? RISC ki frequency ko cycle time mein flip karo (Example 4 jaisa same reciprocal rule), phir master equation apply karo RISC ke apne $N$, CPI aur $T_c$ ke saath. Yahan sab kuch seconds mein rakhte hain kyunki laptop ka baseline already seconds mein hai — matching units matlab end mein koi conversion nahi.

Recall Verify

$\approx 5.78\text{ s}$ vs $12\text{ s}$ → phone laptop ke aadhe se bhi kam time mein finish karta hai. Sanity: CPI $3\times$ drop hua ($4.5\to 1.5$), jo akele $1.3\times$ instruction growth aur $1.11\times$ slower clock ko beat karne ke liye kaafi hai. Gut confirmed.

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Example 8 — Cell H: exam twist, unknown ke liye solve karo

Step 1 — CPI ke liye equation invert karo. $\text{CPI}=\frac{T}{N\times T_c}.$ Yeh step kyun? Unknown ab CPI hai, aur hume target time diya gaya hai — toh hum master equation ko rearrange karte hain CPI isolate karne ke liye na ki forward multiply karne ke liye. Same equation, alag unknown ke liye solve kar rahe hain.

Step 2 — Plug in karo. $\text{CPI}=\frac{4.0\times 10^{-3}\text{ s}}{2.0\times 10^6\times 0.5\times 10^{-9}\text{ s}}=\frac{4.0\times 10^{-3}}{1.0\times 10^{-3}}=\mathrm{4.0.}$ Yeh step kyun? Denominator $N\cdot T_c=2.0\times 10^6\times 0.5\times 10^{-9}\text{ s}=1.0\times 10^{-3}\text{ s}$ woh "time if CPI were 1" hai. Target ko us se divide karne par, ek shot mein, pata chalta hai kitna CPI headroom hai. Note karo ki seconds top aur bottom cancel ho jaate hain, correctly CPI ko dimensionless chodh ke.

Recall Verify

$\text{CPI}=4.0$ ek bahut bada budget hai — RISC chip average 4 cycles per instruction stall kar sakta hai aur phir bhi tie kar sakta hai. Toh is RISC design ke paas enormous slack hai; realistic CPI $\approx 1.2$ ke saath woh CISC baseline ko demolish karega. Reverse-check: $2.0\times 10^6\times 4.0\times 0.5\text{ ns}=4.0\text{ ms}$ ✓.

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Example 9 — Cell I: actual code se instructions count karna (μop expansion)

Step 1 — Instructions count karo. CISC: ek ADD [A],[B] per task → $N_{\text{CISC}}=200,000\times 1=200,000$. RISC: LOAD, LOAD, ADD, STORE = 4 per task → $N_{\text{RISC}}=200,000\times 4=800,000$. Yeh step kyun? $N$ literally executed instructions ka count hai, toh pehle hume code padhna aur count karna hoga. RISC ka load/store rule ADD mein memory operands forbid karta hai, toh ise zaroor 4 lines kharchhni padhengi jahan CISC 1 kharcha karta hai — dekho Addressing Modes.

Step 2 — CISC time. $T_{\text{CISC}}=200,000\times 8\times 1.0\text{ ns}=1.6\times 10^6\text{ ns}=1.6\text{ ms}$ Yeh step kyun? CISC par master equation. Uska ek instruction expensive hai (8 cycles) kyunki internally uska microcode do loads aur ek store hide karta hai. Convert: $1.6\times 10^6\text{ ns}=1.6\text{ ms}$.

Step 3 — RISC time. $T_{\text{RISC}}=800,000\times 1.0\times 0.6\text{ ns}=0.48\times 10^6\text{ ns}=0.48\text{ ms}$ Yeh step kyun? RISC par master equation, counted $N=800,000$ use karke. Uske charon instructions mein se har ek cheap hai (1 cycle, short $T_c$). Convert: $0.48\times 10^6\text{ ns}=0.48\text{ ms}$.

Step 4 — Ratio (slower upar). $\frac{T_{\text{CISC}}}{T_{\text{RISC}}}=\frac{1.6}{0.48}\approx 3.33$ Yeh step kyun? CISC slower hai, toh uska time upar jaata hai; $3.33>1$ padhta hai "RISC is 3.33× faster." Shared ms unit cancel ho jaata hai, ek clean factor deta hai.

Bars ise visually dikhate hain: RISC ka tower 4 bricks tall hai (zyada instructions) lekin har brick short aur fast hai, jabki CISC ek brick, per cycle 8× costly hai. Chhota-brick tower phir bhi chhota nikalta hai.

Recall Verify

RISC $\approx 3.33\times$ faster hai chahe instruction count 4× zyada ho, kyunki CISC ADD — microcode ke andar do memory loads aur ek store chhupa ke — 8 cycles cost karta tha. Yeh Example 1 ki kahani actual assembly ke level par kahi gayi hai, matrix ka cell I close karte hue.

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Wrapping up the matrix

Har cell A–I ke paas ab ek worked example hai: RISC wins (1), CISC wins (2), tie (3), frequency se unit-flipping (4), CPI $=1$ limit (5), zero aur stall-blown inputs (6), ek word problem (7), unknown ke liye solve karna (8), aur real μop expansion se instructions count karna (9). Inme se sab mein ek hi thread hai: sirf ek factor se judge mat karo — hamesha product banao, units dekho, aur ratio se compare karo.

Recall Self-test

Sirf $T=4.0\text{ ms}$, $N=2.0\text{M}$, $T_c=0.5\text{ ns}$ diya ho, CPI nikalo. ::: $\text{CPI}=T/(N\cdot T_c)=4.0\text{ms}/1.0\text{ms}=4.0$ (Example 8). $2.5$ GHz par ek chip — $T_c$ kya hai? ::: $T_c=1/(2.5\times 10^9)=0.4$ ns (Example 4). Aadhi instructions 100 cycles stall karti hain, baaki 1 cost karti hain — effective CPI? ::: $0.5(1)+0.5(101)=51$ (Example 6).