Emerging memories (MRAM, ReRAM, PCM): Exercises — Hardware deep dive

This page is a self-test ladder for the parent topic. Work each problem before opening its solution. Levels climb from L1 Recognition (can you name it?) to L5 Mastery (can you design/decide with it?).

Before we start, one reminder of the symbols we reuse everywhere below, so no symbol is used unexplained:

Definition Symbol glossary (built once, used all page)

$R_{P}, R_{A P}$ — resistance of a magnetic tunnel junction when its two magnetic layers are Parallel / Anti-Parallel. Parallel = low, anti-parallel = high.
$R_{L R S}, R_{H R S}$ — Low / High Resistance State of any resistive cell (ReRAM/PCM). These are the two "physical bits."
$TMR$ — Tunnel Magnetoresistance, a ratio measuring how far apart $R_{A P}$ and $R_{P}$ are: $TMR = (R_{A P} - R_{P}) / R_{P}$ .
$V_{r e a d}$ — the small voltage we apply to read a cell (too small to disturb it).
$R_{L}$ — a fixed load resistor placed in series with the cell to turn its resistance into a readable voltage.
$V_{se n se}$ — the voltage the sense amplifier actually measures at the mid-node of the divider.
$Δ T$ — a temperature rise in kelvin (not an absolute temperature).
$C_{t h}$ — thermal capacitance (joules of heat per kelvin of rise) of the tiny heated volume.

Level 1 — Recognition

Recall Solution 1.1

(a) MRAM → the magnetic orientation of a nanomagnet (parallel vs anti-parallel layers). (b) ReRAM → the presence/absence of a conductive filament inside a metal-oxide. (c) PCM → the atomic phase of the chalcogenide (crystalline vs amorphous). (d) DRAM → stored electric charge on a capacitor (this one is volatile). Why: the first three store a structural/physical state (survives power loss ⇒ non-volatile); only DRAM stores charge (leaks ⇒ volatile).

Recall Solution 1.2

False. Anti-parallel = spins mismatch = few available tunnelling states = high resistance $R_{A P}$ . Parallel = spins line up = low resistance $R_{P}$ . So $R_{A P} > R_{P}$ .

Recall Solution 1.3

RESET. RESET melts the volume then quenches it fast so atoms freeze in disorder → amorphous → high-R. SET only anneals at a lower, intermediate temperature → crystalline → low-R.

Level 2 — Application

Recall Solution 2.1

Plug into the definition: $TMR = \frac{R _{A P} - R _{P}}{R _{P}} = \frac{4.5 - 1.5}{1.5} = \frac{3}{1.5} = 2.0 = 200%.$ Why normalise by $R_{P}$ ? It turns raw ohms into a dimensionless read-margin figure you can compare between devices. 200% means $R_{A P}$ is 3× $R_{P}$ — a comfortable sensing window.

Recall Solution 2.2

The cell and $R_{L}$ form a series pair (see the figure below). By the voltage divider (which is just Ohms Law on a series pair): $V_{se n se} = V_{r e a d} \cdot \frac{R _{L}}{R _{L} + R _{ce l l}} .$ (a) LRS: $V_{se n se} = 0.3 \cdot \frac{10}{10 + 2} = 0.3 \cdot 0.8333 = 0.25 V .$ (b) HRS: $V_{se n se} = 0.3 \cdot \frac{10}{10 + 200} = 0.3 \cdot 0.047619 = 0.0143 V .$ The LRS gives the higher $V_{se n se}$ : a smaller cell resistance drops less of the supply, so more of $V_{r e a d}$ appears across the fixed $R_{L}$ that we measure.

Figure — Emerging memories (MRAM, ReRAM, PCM)

Recall Solution 2.3

Energy = heat capacity × temperature rise: $E = C_{t h} Δ T = (1.2 fJ/K) (600 K) = 720 fJ .$ Why: deposited electrical energy $I^{2} R t$ must supply exactly the thermal energy $C_{t h} Δ T$ to raise the tiny volume by $Δ T$ . That is why RESET (the biggest $Δ T$ ) is PCM's most power-hungry step.

Level 3 — Analysis

Recall Solution 3.1

From 2.2: $V_{L R S} = 0.25 V$ , $V_{H R S} = 0.0143 V$ , so $Δ V_{se n se} = 0.25 - 0.0143 = 0.2357 V .$ Now shrink the window, $R_{H R S} = 20 k Ω$ : $V_{H R S}^{'} = 0.3 \cdot \frac{10}{10 + 20} = 0.3 \cdot 0.3333 = 0.1 V,$ so the new separation is $0.25 - 0.1 = 0.15 V$ . Analysis: the separation dropped from $0.236$ V to $0.15$ V. A smaller $R_{H R S} / R_{L R S}$ ratio (window) squeezes the two sensed voltages together, so the sense amplifier has less margin against noise → more read errors. This is exactly why designers fight for a large resistance window.

Recall Solution 3.2

If $R_{L} ≪ R_{ce l l}$ for both states: $\frac{R _{L}}{R _{L} + R _{ce l l}} \approx \frac{R _{L}}{R _{ce l l}}$ is tiny for both → both $V_{se n se}$ are near zero and nearly equal → no separation.
If $R_{L} ≫ R_{ce l l}$ for both states: the fraction $\approx 1$ for both → both $V_{se n se} \approx V_{r e a d}$ → again nearly equal → no separation.
Best: put $R_{L}$ between $R_{L R S}$ and $R_{H R S}$ (geometric-mean region, $R_{L} \approx R_{L R S} R_{H R S}$ ). Then one state sits on the steep part of the divider curve and the other on the flat part, maximising $Δ V_{se n se}$ .

Level 4 — Synthesis

Recall Solution 4.1

Equate deposited electrical energy to needed thermal energy: $I^{2} R t = C_{t h} Δ T \Rightarrow I^{2} = \frac{C _{t h} Δ T}{R t} .$ Numbers ( $C_{t h} Δ T = 1.0 \times 1 0^{- 15} \cdot 550 = 5.5 \times 1 0^{- 13}$ J; $R t = 12000 \cdot 40 \times 1 0^{- 9} = 4.8 \times 1 0^{- 4} Ω s$ ): $I^{2} = \frac{5.5 \times 1 0 ^{- 13}}{4.8 \times 1 0 ^{- 4}} = 1.1458 \times 1 0^{- 9} A^{2}, I = 1.1458 \times 1 0^{- 9} = 3.386 \times 1 0^{- 5} A \approx 33.9 μ A .$ Why shrinking helps: a smaller cell has a smaller heated volume, so a smaller $C_{t h}$ ; the same $Δ T$ then needs less energy, and (at fixed $R, t$ ) less current. This drives PCM scaling.

Recall Solution 4.2

Choose MRAM (STT). The deciding spec is endurance: a cache is rewritten astronomically often, and MRAM's $\sim 1 0^{15}$ write endurance dwarfs ReRAM ( $\sim 1 0^{6}$ – $1 0^{9}$ ) and PCM ( $\sim 1 0^{8}$ – $1 0^{9}$ ). MRAM also writes in nanoseconds (cache-like speed) and is non-volatile — see Memory Hierarchy for where cache sits. PCM would wear out and burn power (RESET); ReRAM is too noisy/low-endurance for a cache.

Recall Solution 4.3

ReRAM. It is the simplest, cheapest two-terminal cell, packs tightly into a crossbar, and its resistance is analog-tunable (multi-level) — exactly what In-Memory Computing needs to store matrix weights as conductances. Its weaknesses (variability, modest endurance) are tolerable because weights are written rarely and read massively. Its behaviour is the classic Memristor resistance-remembers-history story.

Level 5 — Mastery

Recall Solution 5.1

(a) Geometric mean: $R_{L} = R_{L R S} R_{H R S} = 3 \cdot 300 k Ω = 900 = 30 k Ω.$ (b) Divider $V_{se n se} = V_{r e a d} \cdot \frac{R _{L}}{R _{L} + R _{ce l l}}$ :

LRS: $0.25 \cdot \frac{30}{30 + 3} = 0.25 \cdot 0.909091 = 0.227273 V .$
HRS: $0.25 \cdot \frac{30}{30 + 300} = 0.25 \cdot 0.090909 = 0.022727 V .$ (c) Separation $Δ V_{se n se} = 0.227273 - 0.022727 = 0.204545 V$ . Reference midpoint: $V_{r e f} = \frac{0.227273 + 0.022727}{2} = 0.125 V$ . Why the geometric mean? It balances the divider so one state sits on the steep side and the other on the flat side of the response curve, giving a near-maximal, symmetric gap around $V_{r e f}$ — the most noise-robust placement. See the operating points on the figure.

Recall Solution 5.2

(a) TMR.

A: $(5 - 2) /2 = 1.5 = 150%.$
B: $(3.5 - 1) /1 = 2.5 = 250%.$ Design B has the larger TMR. (b) Sensing separation through $R_{L} = 3 k Ω$ , $V_{r e a d} = 0.2$ V, with $V = 0.2 \cdot \frac{3}{3 + R}$ :
A: $V_{P} = 0.2 \cdot \frac{3}{5} = 0.12$ ; $V_{A P} = 0.2 \cdot \frac{3}{8} = 0.075$ ; $Δ V_{A} = 0.045 V .$
B: $V_{P} = 0.2 \cdot \frac{3}{4} = 0.15$ ; $V_{A P} = 0.2 \cdot \frac{3}{6.5} = 0.092308$ ; $Δ V_{B} = 0.057692 V .$ Design B also gives the larger separation ( $57.7$ mV vs $45$ mV). Reconcile: here bigger TMR did help, but not because TMR magically boosts voltage — it helped because $R_{L} = 3 k Ω$ happens to sit near B's geometric mean ( $1 \cdot 3.5 \approx 1.87 k Ω$ for B vs $2 \cdot 5 \approx 3.16 k Ω$ for A — both reasonably placed). The lesson: TMR predicts the potential window, but the realised $Δ V_{se n se}$ still depends on where you place $R_{L}$ . TMR and load choice are two separate levers.

Recall One-line self-check before you move on

Read window vs write speed are governed by different physics ::: TMR/resistance-window sets read margin; write speed is set by STT critical current / melt-quench / ion-drift — never confuse them. The bit-to-state mapping is fixed by physics ::: False — it is a designer convention; only the size of the resistance window is physical. Best load resistor for reading two states ::: near the geometric mean $R_{L R S} R_{H R S}$ .