Emerging memories (MRAM, ReRAM, PCM): Question bank

This page is pure reasoning — no figures needed.

True or false — justify

TF1. All three technologies (MRAM, ReRAM, PCM) store a bit as electric charge, just like DRAM.

False — they store a physical/structural state (magnetic orientation, atomic phase, or a conductive filament). Because there is no stored charge, there is nothing to leak away, which is exactly why they are non-volatile.

TF2. A high-resistance state must always represent binary "0".

False — the mapping of resistance-state to bit-value is a designer convention. What actually matters is a large, reliable window between the two states, not which one is labelled "1".

TF3. In MRAM, the parallel (P) magnetic alignment gives the higher resistance.

False — parallel alignment lets same-spin electrons tunnel into plenty of matching states, so P is the low-resistance state

R_{P}

; anti-parallel (AP) is the high-resistance state

R_{A P}

TF4. A larger TMR value means the MRAM cell writes faster.

False — TMR is a read margin (how distinguishable the two resistance states are). Write speed is set by the critical current and spin-transfer-torque dynamics, which TMR says nothing about.

TF5. In PCM, the crystalline phase is the high-resistance state.

False — crystalline (ordered lattice) is the low-resistance SET state; the amorphous (disordered) phase is high-resistance. Order lets carriers move easily.

TF6. PCM's SET operation (crystallizing) is the hottest, most power-hungry step.

False — RESET (amorphize) is hotter: it must exceed the melting point and then quench fast. SET only anneals at an intermediate temperature, so RESET dominates write energy.

TF7. ReRAM needs a one-time high-voltage "forming" step before normal operation.

True — the very first use requires a forming voltage to grow the initial conductive filament; afterwards SET/RESET just rebuild or rupture that filament at lower voltage.

TF8. Since MRAM has the best endurance, it is automatically the densest of the three.

False — endurance and density are independent traits. MRAM wins endurance (~

1 0^{15}

writes) but PCM wins density/multi-level storage; each has a different bottleneck.

TF9. Reading a PCM cell can accidentally change its stored bit.

True in principle — that's why reads use a low voltage: too small to cause meaningful Joule Heating, so the phase is never disturbed while sensing.

TF10. All three cells are two-terminal resistive devices.

True — MTJ, filament cell, and phase-change cell are each a single two-terminal resistor, typically paired with one selector transistor (1T1R) inside the array.

Spot the error

SE1. "TMR

= (R_{A P} - R_{P}) / R_{A P}

, normalised by the anti-parallel resistance."

The error is the denominator: TMR is defined as

(R_{A P} - R_{P}) / R_{P}

, normalised by

R_{P}

. Using

R_{P}

keeps the figure comparable to the low-resistance reference state.

SE2. "In Ohm's-law sensing, a high-resistance cell in series with load

R_{L}

gives a higher

V_{se n se}

Wrong direction: in the Voltage Divider

V_{se n se} = V_{r e a d} R_{L} / (R_{L} + R_{ce l l})

, a larger

R_{ce l l}

shrinks the fraction, so a high-R cell gives a lower

V_{se n se}

SE3. "PCM RESET works by holding the cell warm for a long time to melt it slowly."

RESET is a fast melt-quench: heat above melting then cool rapidly so atoms freeze in disorder. Slow cooling would let them re-crystallize into the SET (low-R) state.

SE4. "STT writing flips the free layer at any current — more current just makes it faster."

There is a critical current

I_{c}

; below it the magnetization does not flip at all. Only above

I_{c}

does the spin-transfer torque overcome the barrier.

SE5. "A tiny memory window (

R_{H R S} / R_{L R S} \approx 1.1

) is fine as long as both states are stable."

A small window leaves the sense amplifier almost no voltage gap to resolve, so noise and variability cause read errors even if each state is individually stable.

SE6. "In the Joule-heating relation

Δ T \approx I^{2} R t / C_{t h}

, the

Δ T

is an absolute temperature in Celsius."

Δ T

is a temperature rise in kelvins above ambient, not an absolute temperature. It measures how far above the surroundings the deposited energy pushes the cell.

SE7. "ReRAM's LRS is created by rupturing the filament."

Reversed: SET forms the filament to reach the Low-Resistance State (LRS); RESET ruptures it to reach the High-Resistance State (HRS).

Why questions

WHY1. Why does storing a bit as resistance (not charge) give non-volatility?

Resistance here reflects a stable physical structure (magnet direction, atomic phase, or filament) that persists with no power. Charge, by contrast, leaks through any real insulator, which is why DRAM and Flash Memory eventually lose or must refresh their state.

WHY2. Why is TMR normalised by

R_{P}

instead of quoted in raw ohms?

Normalising turns the read margin into a dimensionless percentage that can be compared across devices of different absolute resistance. Raw ohms would depend on cell size and geometry.

WHY3. Why does a large

R_{H R S} / R_{L R S}

ratio matter for sensing?

In the Voltage Divider read scheme, a bigger ratio widens the

V_{se n se}

gap between the two bit states, giving the sense amplifier more margin against noise and reference drift.

WHY4. Why does electron spin control MTJ resistance at all?

Tunnelling probability depends on how many same-spin states are available in the destination layer. Parallel magnets offer many matching states (easy tunnelling, low R); anti-parallel offer few (hard tunnelling, high R).

WHY5. Why is RESET the PCM scaling bottleneck, and why does shrinking the cell help?

RESET must melt a volume of material, and the energy needed scales with that volume. A smaller cell melts less material, so shrinking directly lowers the RESET current — the driver of PCM scaling.

WHY6. Why is ReRAM favoured for In-Memory Computing and crossbars despite its noise?

Its simple two-terminal resistor maps naturally onto a dense crossbar, where analog resistances can perform Ohm's-law multiply-accumulate in place. The structural simplicity and low write energy outweigh its variability for these workloads.

WHY7. Why does MRAM read faster/more reliably as MgO TMR climbs past 200%?

A higher TMR means

R_{A P}

and

R_{P}

are far apart, so the sensed voltages are clearly separated. The amplifier resolves the two states with less integration time and less error.

WHY8. Why do these memories chase the "universal memory" ideal instead of just improving SRAM?

SRAM is fast but volatile and huge (6 transistors/bit); no charge-based memory simultaneously offers speed, density, and non-volatility. Resistive storage attacks all three at once, which charge scaling cannot.

Edge cases

EC1. What happens to the read scheme if the load

R_{L}

is chosen far below both cell states?

V_{se n se} = V_{r e a d} R_{L} / (R_{L} + R_{ce l l})

becomes tiny for both states, collapsing the gap between them — sensing fails.

R_{L}

should sit between

R_{L R S}

and

R_{H R S}

to maximise separation.

EC2. What if

R_{A P} = R_{P}

in an MTJ (degenerate case)?

TMR

= (R_{P} - R_{P}) / R_{P} = 0

: the two magnetic states are electrically identical, so there is no read margin and the cell cannot store a distinguishable bit.

EC3. What if a PCM RESET pulse deposits energy but is too short to reach the melting rise

Δ T

With

Δ T \approx I^{2} R t / C_{t h}

, too small a

t

(or

I

) never reaches melting, so the material stays crystalline — the RESET simply fails and the old bit survives.

EC4. What if a PCM quench after melting is too slow?

Slow cooling gives atoms time to anneal into the ordered crystalline lattice, so instead of the intended amorphous high-R RESET you accidentally SET the cell to low-R.

EC5. A brand-new ReRAM cell reads a random resistance before any operation — is it broken?

No — before the one-time forming step there is no defined filament, so the resistance is undefined. Forming must run first to create the initial conductive path.

EC6. Endurance is finite (ReRAM/PCM ~

1 0^{6}

–

1 0^{9}

writes). What is the failure mode at end of life?

Repeated switching physically fatigues the cell — filament regions or the phase-change volume degrade — so the two states drift together, the memory window collapses, and reads become unreliable.

EC7. If power is cut mid-write, is the stored bit safe?

The just-written bit may be left in a partial/intermediate physical state (half-formed filament, partially crystallized region), so mid-write power loss can corrupt that cell — non-volatility protects completed states, not in-progress ones.

Recall One-line self-test before moving on

Can you state, for each of MRAM/PCM/ReRAM, (a) what physical thing stores the bit, (b) which state is high-R, and (c) which write step is most expensive? ::: MRAM: magnet orientation, AP is high-R, write cost set by critical current $I_{c}$ . PCM: atomic phase, amorphous is high-R, RESET (melt) most expensive. ReRAM: filament, ruptured HRS is high-R, forming is the one-time high-voltage step.