Emerging memories (MRAM, ReRAM, PCM): Visual walkthrough

Step 1 — What "voltage" and "resistance" even mean

Look at the picture. The tall tank is the voltage source pushing charge down one pipe. The gravel patch is the resistor. Thin flow through thick gravel; thick flow through clear pipe.

Rearranged, the same law says $I = \frac{V}{R}$ (more obstacle ⇒ less flow) and $V = I R$ (more flow through a given obstacle ⇒ bigger push needed). We will use both forms.

Step 2 — Why one resistor alone tells you nothing

Look at the figure: two cells, one low-R (bit "1"), one high-R (bit "0"), both connected alone to the same source. The voltage across each is identical ( $V_{r e a d}$ ). The meter reads the same for both bits. Useless.

Step 3 — Add a partner: two obstacles in a row (series)

Now the current through the whole line is one number: $I = \frac{V _{r e a d}}{R _{L} + R _{ce l l}}$

Numerator $V_{r e a d}$ — the push driving the whole line.
Denominator $R_{L} + R_{ce l l}$ — the combined obstacle.
$I$ — the single flow shared by both resistors.

This is just Ohm's law from Step 1, applied to the pair as one obstacle.

Step 4 — Read the push across the load, not the cell

Look at the figure: the red probe sits on the middle node. The push $V_{r e a d}$ is split — part falls across the cell (top), the rest is $V_{se n se}$ across the load (bottom). Change the cell's resistance and the split moves.

Formula The voltage-divider result — assembled from what we already have

Take the current from Step 3 and apply $V = I R$ to $R_{L}$ : $V_{se n se} = I \cdot R_{L} = \frac{V _{r e a d}}{R _{L} + R _{ce l l}} \cdot R_{L}$ which we tidy to $V_{se n se} = V_{r e a d} \cdot \frac{R _{L}}{R _{L} + R _{ce l l}}$

$V_{r e a d}$ — the total push we applied.
$R_{L}$ in the numerator — the load gets a share of the push equal to its own size…
$R_{L} + R_{ce l l}$ in the denominator — …divided by the total obstacle.
The fraction $\frac{R _{L}}{R _{L} + R _{ce l l}}$ — always between $0$ and $1$ : the slice of the push the load keeps.

WHY this is the central result: now $V_{se n se}$ does depend on $R_{ce l l}$ . A different bit ⇒ a different resistance ⇒ a different slice ⇒ a different, measurable voltage. This is the Voltage Divider identity, and it is the universal read principle for every resistive memory. It answers Step 2's failure exactly by giving the cell a partner to share the push with.

Step 5 — Push it to the two extremes (degenerate cases)

We must check the formula never surprises the reader. Feed it the two limits.

Look at the figure: as $R_{ce l l}$ sweeps from $0$ to $\infty$ , $V_{se n se}$ slides smoothly from $V_{r e a d}$ down to $0$ along a curve. The two real bit-states are two points on that curve.

Step 6 — Put real numbers on it (the worked read)

The one-picture summary

This last figure compresses all six steps: the source pushes $V_{r e a d}$ down a line; the known load $R_{L}$ and the unknown cell $R_{ce l l}$ share that push in series; the probe reads the load's slice $V_{se n se}$ ; and the two bit-states become two clearly separated dots on the divider curve.

Recall Feynman: retell the whole walkthrough to a 12-year-old

A memory bit here is just "hard to push electricity through" (a 1) or "very hard to push through" (a 0). But you can't see how hard something is to push through — so we play a trick. We line up the mystery cell behind a second gravel patch we do know the size of, and we push electricity through both in a single pipe. The total push splits between the two patches. We stick a probe between them and read how much push landed on our known patch. If the mystery cell is easy (a 1), it steals almost none of the push, so our probe reads a big voltage. If the mystery cell is a near-wall (a 0), it hogs the push, and our probe reads almost nothing. Pick the size of your known patch to sit between the two mystery values, and the two answers fly far apart — so far that a simple comparator can tell them instantly. That split-the-push idea is the Voltage Divider, and it is literally how every MRAM, ReRAM and PCM cell gets read.

Recall

Why does a single cell across a source fail to reveal its bit? ::: The source clamps the voltage across it to $V_{r e a d}$ regardless of $R_{ce l l}$ ; nothing shares the push, so the meter reads the same for both bits. In the divider $V_{se n se} = V_{r e a d} R_{L} / (R_{L} + R_{ce l l})$ , what happens as $R_{ce l l} \to 0$ ? ::: $V_{se n se} \to V_{r e a d}$ — the load keeps the whole push. As $R_{ce l l} \to \infty$ ? ::: $V_{se n se} \to 0$ — the giant cell hogs all the push. Why place $R_{L}$ between $R_{L R S}$ and $R_{H R S}$ ? ::: To land the two bit-states on far-apart parts of the divider curve, maximising the memory window the sense amp must resolve.