ROM, PROM, EPROM, EEPROM: Worked examples — Hardware deep dive

This page is the practice arena for the parent topic. The parent explained what each memory is. Here we drill the harder question the exam and the real world actually ask: given a situation, which member of the family survives it — and for how long?

Before any example, one promise: every symbol we use is defined the moment it appears. If you meet $V_{t h}$ , $t_{o x}$ , or "endurance" and feel lost, that is a bug in this page, not in you.

The scenario matrix

Think of every problem this topic can throw as a cell in a grid. One axis is what is being decided (which chip, or how long it lasts, or what physically happens). The other axis is the twist (a limiting case, a degenerate input, a real word problem, an exam trap). Below is the full grid; every example that follows is tagged with the cell it fills.

Cell	What the problem tests	Twist type
C1	Pick the chip: huge volume, fixed data	Real-world word problem
C2	Pick the chip: field-updatable, small data	Real-world word problem
C3	Pick the chip: lab prototype, rewrite often	Real-world word problem
C4	Endurance budget: does the cell survive?	Normal numeric
C5	Endurance with wear leveling	Numeric + fix
C6	Degenerate input: zero rewrites needed	Edge case
C7	Limiting case: retention over decades	Limiting behaviour
C8	Physics twist: what shifts $V_{t h}$ , read as 0/1	Case coverage (both bit states)
C9	Exam trap: EPROM vs EEPROM vs Flash erase	Exam-style twist
C10	Cost crossover: mask cost vs per-unit	Numeric break-even

We will hit all ten cells with ten worked examples. Terms you'll need are built as they arrive; if you want the deeper background, the physics leans on Floating-Gate Transistor, MOSFET and Threshold Voltage, and Fowler–Nordheim Tunneling.

C1 — Millions of units, data never changes

Worked example The router farm

You ship 10 million identical routers. The firmware is finalized and will never change. Which memory?

Forecast: (guess: which of ROM / PROM / EPROM / EEPROM?) …

Step 1 — List what the situation demands. Data is fixed forever → we never need to rewrite. Volume is huge → per-unit cost dominates. Why this step? The right chip is the cheapest one that still meets the (few) requirements. So first find the requirements.

Step 2 — Match to the cheapest member. Mask ROM has a large one-time mask cost (the photomask that etches the bit pattern into silicon) but a near-zero per-unit cost. At 10 million units that fixed cost is spread paper-thin. Why this step? Cost per bit is lowest for Mask ROM only at scale — exactly our scale.

Answer: ROM (Mask ROM).

Verify: Immutable data ✓ (fine, never updated). Cheapest at volume ✓. Bonus: it can't be corrupted by a stray write, since there is physically no write path. Sanity check passes.

C2 — Small updates in the field

Worked example The calibration byte

A shipped microcontroller must occasionally update a calibration constant (a few bytes) while installed in a customer's machine — no UV lamp, no chip removal. Which memory?

Forecast: …

Step 1 — Extract the hard constraints. "In the field" ⇒ must rewrite in-circuit. "A few bytes" ⇒ fine granularity. "No UV lamp" ⇒ cannot be UV-erased. Why this step? Each phrase eliminates candidates; naming them makes the elimination visible.

Step 2 — Eliminate. ROM/PROM: can't rewrite at all → out. EPROM: needs UV light + whole-chip erase + removal → out. Why this step? Only survivors can be the answer; kill the impossible first.

Answer: EEPROM — erases electrically, byte-by-byte, in-circuit.

Verify: In-circuit ✓, per-byte ✓, no UV ✓. All three constraints satisfied by exactly one member. Uniqueness = confidence.

C3 — Lab prototype, rewrite often, cost irrelevant

Worked example The 1980s dev board

You are developing firmware on a bench. You will reflash it hundreds of times. Cost per chip doesn't matter; a UV eraser sits on your desk. Which memory (period-appropriate)?

Forecast: …

Step 1 — Requirements. Rewrite hundreds of times ⇒ rules out PROM (one write) and ROM (zero writes). UV eraser available ⇒ whole-chip UV erase is acceptable. Why this step? Endurance need (hundreds of cycles) sets the floor; a chip rated for ~100s–1000s of writes suffices.

Step 2 — Choose. EPROM is reprogrammable many times, erased by UV through its quartz window. Perfect for the erase-and-retry development loop. Why this step? EEPROM would also work but historically cost more; EPROM was the classic dev choice.

Answer: EPROM.

Verify: Hundreds of rewrites ≤ EPROM endurance ✓. UV erase acceptable ✓. Matches the parent's "pencil on paper, erase with UV light" analogy.

C4 — Endurance budget: does one cell survive?

First, the term. Endurance = the number of write/erase cycles a single cell can take before its oxide wears out and it stops reliably storing a bit. Rated as a count, e.g. $1 0^{5}$ cycles.

C5 — Same job, but spread the wear

Worked example Wear leveling to the rescue

Same device, same once-a-minute writes. Now you rotate the write across $N = 1000$ different byte locations instead of hammering one. New lifetime?

Forecast: …

Step 1 — Effective total cycles. Endurance is per cell. With 1000 cells each rated $1 0^{5}$ : $1 0^{5} \times 1000 = 1 0^{8} total tolerable writes$ Why this step? Rotating the target means each individual cell only sees $1/1000$ of the writes, so the system tolerates 1000× more.

Step 2 — Lifetime. $\frac{1 0 ^{8}}{525 , 600} \approx 190 years$ Why this step? Same division as C4, with the multiplied endurance.

Answer: ~190 years. From 69 days to two centuries by rotating addresses — this trick is called wear leveling.

Verify: $190 \approx 0.190 \times 1000$ ✓ (exactly 1000× the C4 answer, as expected). Related idea in Flash Memory, where wear leveling is essential.

C6 — Degenerate input: zero rewrites needed

Worked example The "how many writes?" trap

A product's data is written once at the factory and never again — but the marketing team insists on "an updatable chip, just in case." Endurance needed: 0 further writes. What's the engineering-optimal choice, ignoring politics?

Forecast: …

Step 1 — Interpret the degenerate case. Required rewrite count $= 0$ . Any endurance value $\geq 0$ satisfies it — even a chip that literally can't be rewritten. Why this step? When the requirement is the minimum possible (zero), the constraint that usually forces expensive chips disappears.

Step 2 — Pick the cheapest that meets zero-rewrite. At high volume, Mask ROM (0 writes) is cheapest and immune to corruption. At low/medium volume where a mask is too costly, PROM (write once, then permanent) fits. Why this step? With rewrites unneeded, cost and immutability win; flexibility is wasted money.

Answer: ROM at large volume, PROM at small volume. The "just in case" flexibility is a cost with no payoff.

Verify: Requirement $0 \leq$ endurance of ROM ( $0$ ) ✓ and PROM ( $1$ ) ✓. Both legal; choose by cost. This edge case is exactly the parent's first [!mistake] about "flexibility always better."

C7 — Limiting behaviour: retention over decades

Here the star is retention — how long trapped charge stays on the floating gate with the power off. The parent gave the leakage law; we read its limiting behaviour.

Worked example Does the data survive 10 years unpowered?

The floating-gate leakage current obeys $I_{l e ak} \propto exp (- \frac{4 2 m ^{*} ϕ _{B}^{3/2}}{3 ℏ q E} t_{o x})$ where $t_{o x}$ = oxide thickness, $ϕ_{B}$ = barrier height, $E$ = electric field, and the rest are physical constants. Suppose a design change doubles the oxide thickness $t_{o x}$ . Qualitatively, what happens to leakage and hence retention?

Forecast: (leakage halves? doubles? shrinks hugely?) …

Step 1 — Locate $t_{o x}$ in the formula. It sits inside the exponent, multiplied by a negative constant $- k$ (bundle everything else into $k > 0$ ): $I_{l e ak} \propto e^{- k t_{o x}}$ . Why this step? The behaviour of an exponential is decided entirely by what's in its exponent.

Step 2 — Double $t_{o x}$ . $e^{- k (2 t_{o x})} = (e^{- k t_{o x}})^{2}$ Leakage isn't halved — it is squared (a tiny number squared is vastly tinier). Why this step? Doubling inside a negative exponent squares the (already small) leakage factor. That is the power of exponential decay.

Answer: Leakage drops enormously; retention leaps well past the ~10-year target. Thicker oxide ⇒ exponentially better retention.

Verify (numeric sanity): take $k t_{o x} = 20$ . Then $e^{- 20} \approx 2.06 \times 1 0^{- 9}$ ; doubling gives $e^{- 40} \approx 4.25 \times 1 0^{- 18}$ — the ratio is $e^{- 20} \approx 2.06 \times 1 0^{- 9}$ , i.e. leakage falls by ~9 orders of magnitude ✓. Exponential, not linear — the whole reason non-volatile memory works. See Fowler–Nordheim Tunneling.

C8 — Both bit states: what the trapped charge does

This example covers both logic values, so no reader hits an unshown case.

Worked example Charge on the gate ⇒ which bit?

A floating-gate cell is read by applying a fixed read voltage $V_{r e a d}$ to its control gate and checking whether the transistor conducts. The transistor conducts only if $V_{r e a d}$ exceeds its threshold voltage $V_{t h}$ (the gate voltage needed to switch the transistor on). Trapped electrons on the floating gate raise $V_{t h}$ . Work out the read result for both states.

Forecast: …

Step 1 — Erased cell (no trapped electrons). $V_{t h}$ is low. Since $V_{r e a d} > V_{t h}$ , the transistor conducts → the sense circuit reads this as, say, logic 1. Why this step? Establish the baseline state before any charge is added — look at the left cell in the figure (green, low barrier).

Step 2 — Programmed cell (electrons trapped). The trapped negative charge repels the channel, raising $V_{t h}$ above $V_{r e a d}$ . Now $V_{r e a d} < V_{t h}$ , the transistor stays off → reads as logic 0. Why this step? This is the other case; look at the right cell (red, raised barrier) — the read line no longer clears the threshold.

Answer: Erased = conducts = 1; programmed = blocked = 0. Both bit states covered, both explained by the same $V_{t h}$ shift.

Verify: In Step 1, $V_{r e a d} - V_{t h, erased} > 0$ (conducts) ✓. In Step 2, $V_{r e a d} - V_{t h, prog} < 0$ (blocked) ✓. The sign of $(V_{r e a d} - V_{t h})$ is the stored bit. Deeper: MOSFET and Threshold Voltage.

C9 — Exam trap: three erase mechanisms, don't confuse them

Worked example Which chip matches which erase story?

Match each description to EPROM, EEPROM, or Flash: (a) erased in large blocks, electrically; (b) erased whole-chip by UV light through a quartz window; (c) erased byte-by-byte, electrically, in-circuit.

Forecast: …

Step 1 — Anchor on the erase granularity and method. The trap is that (a) and (c) are both electrical. The distinguisher is how much is erased at once. Why this step? Names differ by one letter; the reliable discriminator is the erase workflow, not the acronym.

Step 2 — Assign. (b) UV + whole-chip → EPROM. (c) electrical + per-byte → EEPROM. (a) electrical + block → Flash (block-erasable EEPROM cousin, optimized for density). Why this step? Each description now has exactly one home.

Answer: (a) Flash, (b) EPROM, (c) EEPROM.

Verify: The extra "E" in EEPROM = Electrically (vs EPROM's UV) ✓. Flash = block-erase for density ✓. Matches the parent's two "steel-manned" mistakes about EPROM≠EEPROM and Flash≠EEPROM. More at Flash Memory.

C10 — Cost crossover: mask ROM vs EEPROM break-even

Worked example At what volume does Mask ROM win?

Mask ROM: one-time mask cost $\$ 50{,}000 $, t h e n$ $0.10 $p er u ni t . E E P R O M (n o ma s k) :$ $0.60 $p er u ni t . F i r m w a r e i s f i x e d, so b o t h w or k f u n c t i o na l l y . A b o v e w ha tq u an t i t y$ Q$ is Mask ROM cheaper?

Forecast: (a few thousand? a hundred thousand?) …

Step 1 — Write both total-cost lines. Mask ROM: $C_{R O M} (Q) = 50, 000 + 0.10 Q$ . EEPROM: $C_{E E} (Q) = 0.60 Q$ . Why this step? Total cost = fixed + per-unit × quantity; comparing chips means comparing these lines.

Step 2 — Set equal, solve for the crossover. $50, 000 + 0.10 Q = 0.60 Q \Rightarrow 50, 000 = 0.50 Q \Rightarrow Q = 100, 000$ Why this step? The break-even is where the two total costs match; beyond it, the lower slope (Mask ROM) wins.

Answer: Above 100,000 units, Mask ROM is cheaper. Below it, EEPROM wins despite higher per-unit cost, because it avoids the mask fee.

Verify: At $Q = 100, 000$ : $C_{R O M} = 50, 000 + 10, 000 = 60, 000$ ; $C_{E E} = 60, 000$ — equal ✓. At $Q = 200, 000$ : ROM $= 70, 000 <$ EEPROM $= 120, 000$ ✓. This is the quantitative version of C1's "cheapest at scale."

The matrix, now filled

Recall Self-test: name the deciding factor

C1 vs C10 decide by? ::: Volume — per-unit cost dominates only at scale (break-even ~100k units). C4 vs C5 differ by? ::: Wear leveling — spreading writes over N cells multiplies endurance by N. C7's key insight? ::: Leakage is exponential in oxide thickness, so retention improves enormously with modest oxide changes. C8's stored bit is the sign of what? ::: $V_{r e a d} - V_{t h}$ — trapped charge raises $V_{t h}$ , flipping conduction.

See also: Volatile vs Non-Volatile Memory, RAM (SRAM, DRAM), Memory Hierarchy, Boot Firmware and BIOS.