ROM, PROM, EPROM, EEPROM: Visual walkthrough — Hardware deep dive

We will need three prerequisites, and we build each one when it appears: what a transistor threshold is, what a floating gate adds, and what tunneling is.

Step 1 — What a plain switch (MOSFET) actually is

WHAT. Before any memory, we need one idea: a transistor is a voltage-controlled switch. It has three parts that matter to us: a source and drain (two terminals current might flow between) and a gate (a control knob sitting just above the channel between them).

WHY this first. A memory cell has to answer one yes/no question when read: does current flow, or not? Everything else on this page exists only to change that answer. So we must first see what decides whether current flows.

PICTURE (figure s01). In figure s01, current wants to run from source to drain (black), but a barrier region blocks it. The gate voltage $V_{G}$ (red — the one thing we control) pulls electrons up into the channel. Only when $V_{G}$ is high enough does a conducting bridge form.

Step 2 — Add the floating gate: an island for electrons

WHAT. Now we insert a second gate between the control gate and the channel. Crucially, this second gate touches nothing — it is surrounded on all sides by insulating oxide. It is electrically an island. We call it the floating gate.

WHY. In Step 1, $V_{t h}$ was a fixed property of the silicon. To store a bit we need $V_{t h}$ to be changeable — and to stay changed with the power off. An isolated island that can hold electric charge is exactly that: put charge on it and it stays; the charge silently biases the transistor.

PICTURE (figure s02). In figure s02, two gates are stacked. The top control gate is the knob we touch. The middle floating gate (red) is the island, drawn floating inside a moat of oxide, connected to nothing.

Step 3 — Trapped charge moves the tipping point

Before symbols, one constant we will lean on from here on:

WHAT. Say we push a pile of electrons onto the floating gate. Electrons carry negative charge. That negative island sits right above the channel and repels the electrons the control gate is trying to attract into the channel. So the control gate must now push harder to turn the transistor on. In symbols, $V_{t h}$ goes up.

WHY. This is the whole payoff. The two states of the cell are simply:

No electrons on floating gate → low $V_{t h}$ → at read voltage the cell conducts → call it "1".
Electrons trapped on floating gate → high $V_{t h}$ → at the same read voltage the cell stays off → call it "0".

The bit is the amount of trapped charge.

PICTURE (figure s03). Figure s03 shows two versions of the transistor side by side, and one $V_{t h}$ number-line. The read voltage $V_{r e a d}$ (from Step 1) is a fixed vertical mark (red). When trapped charge shifts $V_{t h}$ to the right of $V_{r e a d}$ , the cell is off.

Formula The threshold shift

$Δ V_{t h} = - \frac{Q _{F G}}{C _{C G}}$

$Δ V_{t h}$ — how far the tipping point moved (volts).
$Q_{F G}$ — the signed total charge on the floating gate (coulombs). Since we store electrons, and electrons are negative, $Q_{F G} < 0$ ; the minus sign in front then makes $Δ V_{t h} > 0$ , i.e. the tipping point moves up/right — exactly what the WHAT paragraph predicted. (If you prefer to count electrons, write $Q_{F G} = - n q$ with $n$ the electron count and $q$ the elementary charge just defined; then $Δ V_{t h} = + n q / C_{C G}$ .)
$C_{C G}$ — the capacitance between the control gate and the floating gate (farads); a geometry constant.

WHY division? Voltage across a capacitor is charge divided by capacitance ( $V = Q / C$ ). The floating-gate charge sits on a capacitor formed with the control gate, so its effect on the sensed voltage scales as $Q_{F G} / C_{C G}$ .

Step 4 — Writing: how do we get electrons onto a walled island?

WHAT. The floating gate is surrounded by oxide the electrons "cannot" cross. To write, we cheat: apply a large voltage on the control gate. This bends the energy landscape so steeply that electrons tunnel through the thin oxide onto the island (and/or are shot across as "hot" electrons). This is Fowler–Nordheim tunneling.

WHY a high voltage and not the normal read voltage? Because the oxide is a wall. At ordinary voltages the wall is impassable (that's what makes storage last). Only a strong electric field tilts the wall thin enough for electrons to slip through. So writing needs high voltage; reading (at $V_{r e a d}$ ) uses gentle voltage that leaves the stored charge alone.

PICTURE (figure s04). Figure s04 draws the oxide barrier as an energy "hill". With no field it is a tall rectangular wall. With a big field applied, the wall tilts into a thin triangle — and an electron's wave leaks through the thin tip.

Step 5 — Retention: why the electrons don't just leak back

WHAT. Now the write voltage is gone. The electrons are on the island. Do they stay? They can leak back by the same tunneling — but at read/idle there is almost no field, so the barrier is thick and the leak is tiny. We now quantify "tiny."

WHY we care about the exact shape. If leakage were merely slow, we'd worry. But it turns out to fall exponentially with the barrier thickness — and exponential decay is astronomically fast in the exponent. That single fact is what buys us years.

PICTURE (figure s05). Figure s05 shows the electron wave entering the oxide and its amplitude collapsing along the way — drawn as a decaying curve $ψ (x)$ (red) inside the barrier. A thick barrier means the wave is essentially gone by the far side.

Step 6 — From wave decay to the 10-year number

First, three quantities this step needs, defined before use:

Definition Electric field

$E$ , leak current $I_{l e ak}$ , survival probability $P$

The ==electric field $E$ == is how steeply voltage changes across the oxide: for a gate voltage $V_{g a t e}$ dropped across thickness $t_{o x}$ , $E = V_{g a t e} / t_{o x}$ (units volts per metre). It points across the oxide, and its direction sets whether electrons are pushed onto the island (write) or off it (erase); at idle $V_{g a t e} \approx 0$ so $E \approx 0$ .
The ==survival probability $P$ == is the chance a single tunneling attempt gets the electron across the wall. From figure s05, $P \propto ∣ ψ (t_{o x}) ∣^{2}$ — the square of the surviving wave amplitude.
The ==leak current $I_{l e ak}$ == is the trapped charge draining per second. It equals the electron attempt-rate $ν$ (how many times per second an electron bangs on the wall, of order $1 0^{12}$ – $1 0^{15} s^{- 1}$ ) times $q$ times $P$ : $I_{l e ak} = q ν P$ . So the whole temperature-free physics of leakage lives inside $P$ .

WHAT. For a flat wall of height $ϕ_{B}$ and width $t_{o x}$ , the survival probability is $P \propto ∣ ψ (t_{o x}) ∣^{2} = e^{- 2 κ t_{o x}}$ . Under a real field the wall is a triangle, so $κ$ is not constant — it shrinks with depth, because the tilted wall's height above the electron falls off. We must add up the decay over the whole triangle.

WHY integrate — the explicit calculation. Let the local barrier height at depth $x$ be $ϕ (x) = ϕ_{B} - q E x$ (the tilt subtracts energy $q E x$ ). It reaches zero at the exit point $x_{0} = \frac{ϕ _{B}}{q E},$ so the triangle has width $x_{0}$ . The total decay exponent is the sum (integral) of the local rate $2 κ (x) = \frac{2 2 m ^{*}}{ℏ} ϕ (x)$ across it: $G = \int_{0}^{x_{0}} \frac{2 2 m ^{*}}{ℏ} ϕ_{B} - q E x d x .$ Do the integral by u-substitution. Let $u = ϕ_{B} - q E x$ , so $d u = - q E d x$ , i.e. $d x = - \frac{d u}{q E}$ . Limits: $x = 0 \Rightarrow u = ϕ_{B}$ ; $x = x_{0} \Rightarrow u = 0$ . Then $G = \frac{2 2 m ^{*}}{ℏ} \int_{ϕ_{B}}^{0} u (- \frac{d u}{q E}) = \frac{2 2 m ^{*}}{ℏ q E} \int_{0}^{ϕ_{B}} u^{1/2} d u .$ Using $\int_{0}^{ϕ_{B}} u^{1/2} d u = [\frac{2}{3} u^{3/2}]_{0}^{ϕ_{B}} = \frac{2}{3} ϕ_{B}^{3/2}$ , $G = \frac{2 2 m ^{*}}{ℏ q E} \cdot \frac{2}{3} ϕ_{B}^{3/2} = \frac{4 2 m ^{*} ϕ _{B}^{3/2}}{3 ℏ q E} .$ So the survival probability is $P \propto e^{- G}$ , giving $I_{l e ak} = q ν P \propto exp (- \frac{4 2 m ^{*} ϕ _{B}^{3/2}}{3 ℏ q E}) .$

Reading the true form vs. the parent note. Notice $t_{o x}$ has cancelled out of the exponent above: for a pure triangular barrier the width is fixed by $E$ and $ϕ_{B}$ ( $x_{0} = ϕ_{B} / q E$ ), so the standard Fowler–Nordheim exponent depends on $E$ and $ϕ_{B}$ only — there is no free-standing $t_{o x}$ factor. The parent note writes the exponent with a $t_{o x}$ present; that form is the thick-barrier / low-field regime, where the field does not tilt the wall all the way to zero inside the oxide. Then the electron crosses the full width $t_{o x}$ at a roughly constant rate $2 κ$ , giving the rectangular-barrier result $I_{l e ak} \propto e^{- 2 κ t_{o x}} = exp (- \frac{2 2 m ^{*} ϕ _{B}}{ℏ} t_{o x}),$ which does carry a linear $t_{o x}$ . The two forms are the two limits of the same wave-decay picture (triangular tip for the strong-field write, thick rectangular wall for idle retention); use the $t_{o x}$ form when reasoning about how oxide thickness sets retention, and the $E, ϕ_{B}$ form when reasoning about the write field.

A concrete 10-year estimate (idle retention). Use the thick-wall form, since at idle $E \approx 0$ . Plug in silicon-dioxide numbers: barrier $ϕ_{B} \approx 3.1 eV = 3.1 \times 1.6 \times 1 0^{- 19} J$ , effective mass $m^{*} \approx 0.5 m_{e}$ with $m_{e} = 9.11 \times 1 0^{- 31} kg$ , $ℏ = 1.05 \times 1 0^{- 34} J\cdots$ , and oxide $t_{o x} \approx 9 nm = 9 \times 1 0^{- 9} m$ . Then $2 κ = \frac{2 2 m ^{*} ϕ _{B}}{ℏ} \approx \frac{2 2 ( 0.5 ) ( 9.11 \times 1 0 ^{- 31} ) ( 4.96 \times 1 0 ^{- 19} )}{1.05 \times 1 0 ^{- 34}} \approx 1.4 \times 1 0^{10} m^{- 1},$ so the exponent is $2 κ t_{o x} \approx (1.4 \times 1 0^{10}) (9 \times 1 0^{- 9}) \approx 125$ . That is enormous. With attempt-rate $ν \sim 1 0^{13} s^{- 1}$ , the survival per attempt is $P \sim e^{- 125} \approx 1 0^{- 54}$ , so the escape rate per electron is $ν P \sim 1 0^{13} \times 1 0^{- 54} = 1 0^{- 41} s^{- 1}$ — an escape time far, far beyond the age of the universe for the deepest electrons. Real cells are engineered to sit right where the aggregate charge loss crosses the "still readable" line at about $1 0^{8.5} s \approx 10$ years; the point of the estimate is that the exponent is a few hundred, and shaving it (thinner oxide) or padding it (thicker oxide) swings retention by many orders of magnitude. That giant exponent is why the number is "years," not "seconds."

PICTURE (figure s06). Figure s06 shows trapped charge $Q_{F G}$ decaying in time — a gentle exponential droop. The horizontal line marks the minimum charge still readable as "0"; where the curve crosses it (red mark) is the end of retention ≈ 10 years.

Step 7 — The edge cases (every scenario shown)

WHAT & WHY. A good walkthrough must never leave the reader in an unshown situation. Here are all the degenerate and limiting cases of the trick, each traced back to a symbol we defined.

Zero trapped charge ( $Q_{F G} = 0$ ). Then $Δ V_{t h} = - 0/ C_{t o t a l} = 0$ . The tipping point never moved; the cell always reads "1". This is a blank/erased cell — correct and expected.
Erasing an EPROM (UV light). UV photons add energy to the trapped electrons so they clear the barrier without a field ( $E \approx 0$ but energy comes from light instead). But light floods the whole chip, so every cell empties at once → whole-chip erase (the parent note's quartz window).
Erasing an EEPROM (reverse field). Set $E$ the other way (reverse $V_{g a t e}$ ); electrons tunnel off the island. Because you can address one byte's gate, this is byte-erase, in-circuit.
Very thin oxide ( $t_{o x} \to 0$ ). In the thick-wall form the exponent $2 κ t_{o x} \to 0$ , so $I_{l e ak}$ is no longer suppressed — charge leaks in seconds and retention collapses. This is the physical wall on shrinking cells.
Very high idle field ( $E$ large even at rest). In the triangular form $x_{0} = ϕ_{B} / q E$ shrinks and the exponent $\propto 1/ E$ falls, so leak grows. Retention needs $E \approx 0$ (i.e. $V_{g a t e} \approx 0$ ) when idle.
Zero field limit ( $E \to 0$ ). In the triangular form $x_{0} = ϕ_{B} / q E \to \infty$ : the triangle never reaches the far side, tunneling switches off, and only the thick-wall $e^{- 2 κ t_{o x}}$ path remains — exactly the idle-retention regime. The two forms meet here consistently.
High temperature. Even with a fat oxide, thermal emission ( $exp (- ϕ_{B} / k_{B} T)$ ) rises with $T$ and can drain the gate — retention specs are always tied to a stated temperature.
Endurance limit. Each write forces electrons violently through the oxide, chipping the wall (trapping defects that lower the effective $ϕ_{B}$ ). After $1 0^{4}$ – $1 0^{6}$ writes the oxide is too damaged to hold charge — hence finite endurance, not infinite.

PICTURE (figure s07). Figure s07 is one field diagram showing three field directions: near-zero (store, red = safe), forward-strong (write), reverse-strong (EEPROM erase); plus a UV arrow (EPROM erase).

The one-picture summary

Figure s08 compresses all seven steps: a switch whose tipping point $V_{t h}$ is dragged left/right by charge on a walled island (red), that charge placed by tunneling under high field and held by an exponentially thick wall at idle.

Recall Feynman retelling — say it in plain words

A transistor is a switch with a tipping point: give the gate more than $V_{t h}$ volts and current flows. Now sneak a tiny metal island under the gate, wrapped completely in insulator. If we hide some electrons on that island, their negative charge fights the gate, so it takes more voltage to switch on — the tipping point moves up. We read the cell at a fixed gentle voltage $V_{r e a d}$ : island empty ⇒ it switches ⇒ "1"; island loaded ⇒ it stays off ⇒ "0". To write, we blast a high voltage so electrons tunnel through the thin insulator (thickness $t_{o x}$ ) onto the island. To keep the bit, we remove the voltage — now the insulator is a thick wall, and quantum-mechanically the electron's wave dies off exponentially inside it, so escape is suppressed by a factor like $1 0^{- 17}$ or smaller, giving ten years of memory with the power off — as long as it doesn't get too hot, since heat lets electrons hop over the wall instead. To erase, EPROM floods the chip with UV to kick every electron out at once, while EEPROM reverses the field to peel electrons off byte-by-byte in place. And because each violent write bruises the wall, we only get so many writes — that's endurance.

Recall Rapid self-check

What single physical quantity is the stored bit? ::: The amount of charge $Q_{F G}$ trapped on the floating gate. Why does trapped charge encode a bit? ::: It shifts $V_{t h}$ by $- Q_{F G} / C_{t o t a l}$ (positive shift for trapped electrons), changing whether the cell conducts at the fixed read voltage $V_{r e a d}$ . Why does retention last ~10 years and not seconds? ::: Leakage is tunneling, and the survival probability is $e^{- (big number)}$ ; the exponent (like $2 κ t_{o x} \approx 125$ for a 9 nm oxide) is so large that the escape rate is astronomically small. Why does writing need high voltage but reading doesn't? ::: High voltage makes a large field $E = V_{g a t e} / t_{o x}$ that tilts the oxide barrier into a thin triangle you can tunnel through; the low read voltage keeps $E$ tiny so the wall stays thick and stored charge stays put. Besides tunneling, what else drains the floating gate, and when does it matter? ::: Thermal (thermionic) emission over the barrier, $\propto exp (- ϕ_{B} / k_{B} T)$ — negligible at room temperature but dominant at high temperature, which is why retention is quoted at a stated temperature. What's the difference between EPROM and EEPROM erase in one line? ::: UV clears the whole chip at once; a reverse electric field clears EEPROM electrically, byte-by-byte, in-circuit.