Worked examples — Hazards (static and dynamic) in combinational logic

Before anything else, let us pin down the vocabulary in plain words so no symbol sneaks in undefined.

---

The scenario matrix

Every hazard problem you will ever be handed falls into one of these cells. Our job is to hit all of them.

Cell	Case class	What makes it tricky
A	Static-1 hazard (SOP)	output holds $1$, dips to $0$
B	Static-0 hazard (POS)	output holds $0$, spikes to $1$
C	No hazard (degenerate)	adjacent cells already share a term — nothing to fix
D	Two hazards in one function	more than one adjacency needs covering
E	Dynamic hazard	one input change, $\ge 3$ output flips
F	Timing / limiting values	glitch width shrinks to zero as delays match
G	Real-world word problem	glitch feeds an asynchronous load
H	Exam twist	"the redundant term is redundant, delete it" trap

Cell C is the one students forget: not every adjacency glitches. We prove it too.

---

Cell A — Static-1 hazard in SOP

1. Evaluate both endpoints. Why this step? A hazard needs the initial and final values equal — otherwise the change is a legitimate transition, not a glitch.

   • $B=1$: $F=(1)(1)+(0)(1)=1$.
   • $B=0$: $F=(1)(0)+(1)(1)=1$. Both are $1$ ⇒ static-1 candidate. ✔

2. Find the reconvergent paths of the changing input $B$. Why? The glitch source is always one input, two delays.

   • Path 1: $B\to$ AND gate $AB$ (direct, fast).
   • Path 2: $B\to$ inverter $\to \bar{B}\to$ AND gate $\bar{B}C$ (slow by one gate delay).

3. Trace the bad window. Why? We want the exact instant both product terms read $0$.

   • $B$ falls: $AB$ drops to $0$ immediately.
   • $\bar{B}$ has not risen yet, so $\bar{B}C$ is still $0$ for one inverter-delay.
   • Both terms $0$ ⇒ $F$ momentarily $0$. Glitch $1\to 0\to 1$. See figure.

4. Cure with the consensus term. Why? We need a term that stays $1$ through the change so the output never depends on the handoff. Consensus of $AB$ and $\bar{B}C$ (drop the variable $B$ that appears true in one, complemented in the other) is $AC$. $F=AB+\bar{B}C+\underset{=1\text{ when }A=C=1}{\underbrace{AC}}$

See Karnaugh Maps and Prime Implicants and Consensus Theorem and Redundancy for the algebra behind $AC$.

---

Cell B — Static-0 hazard in POS

1. Evaluate endpoints. Why? Same reasoning — need equal ends.
   • $B=0$: $G=(0+0)(1+0)=(0)(1)=0$.
   • $B=1$: $G=(0+1)(0+0)=(1)(0)=0$. Both $0$ ⇒ static-0 candidate. ✔
2. Reconvergent paths of $B$. $B$ enters factor 1 directly; $\bar{B}$ enters factor 2 through an inverter (slow).
3. Bad window. As $B$ rises: factor 1 becomes $1$ immediately; factor 2 is $(\bar{B}+C)=(1+0)=1$ still, because $\bar{B}$ hasn't fallen yet. Briefly both factors are $1$ ⇒ $G$ spikes to $1$. Glitch $0\to 1\to 0$.
4. Cure with consensus sum. Why a sum? In POS the output is a product of factors; to pin it to $0$ we need one factor that is $0$ during the change. Consensus of $(A+B)$ and $(\bar{B}+C)$ is $(A+C)$. $G=(A+B)(\bar{B}+C)\underset{=0\text{ when }A=C=0}{\underbrace{(A+C)}}$

---

Cell C — The degenerate "no hazard" case

1. Endpoints. $B=1$: $H=(1)(1)+(1)(1)=1$. $B=0$: $H=(1)(0)+(1)(1)=1$. Equal ⇒ candidate.
2. Paths of $B$. $B$ enters only one term, $AB$. There is no inverter on $B$ and no second $B$-path. So $B$ is not reconvergent through unequal delays here.
3. Trace. As $B$ falls, $AB\to 0$, but $AC=(1)(1)=1$ never moved — it holds $H=1$ the whole time.
4. Conclusion. No handoff, no window, no glitch. The term $AC$ already plays the covering role that $AC$ played as a fix in Cell A.

---

Cell D — Two hazards, one function

1. List the pairwise consensus terms. Why? Each adjacent 1-pair sitting in different prime implicants is a potential glitch, and consensus of that pair covers it.
   • Consensus of $\bar{A}\bar{B}$ and $AC$ (variable $A$) $=\bar{B}C$.
   • Consensus of $AC$ and $B\bar{C}$ (variable $C$) $=AB$.
   • Consensus of $\bar{A}\bar{B}$ and $B\bar{C}$ (variable $B$) $=\bar{A}\bar{C}$.
2. Check each is a real transition point. Why? Only add a term if the pair are genuinely adjacent 1s handed off between terms. Here all three pairs are adjacent (each pair differs in exactly the eliminated variable with the other two literals compatible), so all three consensus terms are needed.
3. Hazard-free cover. $F=\bar{A}\bar{B}+AC+B\bar{C}+\bar{B}C+AB+\bar{A}\bar{C}$

---

Cell E — A dynamic hazard

1. Sequence the arrivals. Why? Each unequal-delay arrival of the same logical change flips the output as it lands.

   • $t=1$: $Y$ flips (1st).
   • $t=2$: $Y$ flips (2nd).
   • $t=3$: $Y$ flips (3rd).

2. Count. $Y$ changes 3 times — e.g. $0\to 1\to 0\to 1$. Expected changes $=1$, actual $=3(\ge 3,\text{ odd})$ ⇒ dynamic hazard. ✔

3. Net change / parity. $3$ is odd, so the final value differs from the initial — the true single transition did happen; the extra $2$ flips are a spurious spike pair. See figure.

4. Cure. Why not consensus? A single consensus term cannot force monotonic switching across three paths. You must redesign to a two-level network (or a provably hazard-free multi-level one) covering every adjacency — see the parent's dynamic-hazard note.

---

Cell F — Limiting / timing values

1. Compute the width. $w=5-2=3\text{ns}$. Why? The output is wrong exactly while the slow path lags the fast path.
2. Limiting case $t_{\text{path2}}\to t_{\text{path1}}$. Then $w\to 0$: the glitch shrinks to zero width and effectively vanishes. Why care? This is why perfectly balanced delays seem hazard-free — but you can never guarantee balance across temperature and voltage, so you still design in the consensus term.
3. Degenerate zero case. If $t_{\text{path2}}<t_{\text{path1}}$ (impossible for direct-vs-inverter, but possible in general routing), $w\le 0$ ⇒ no glitch, or the roles swap.

---

Cell G — Real-world word problem

1. Identify the load type. Why? Synchronous vs Asynchronous Circuits: asynchronous inputs act the instant they see a level — they do not wait for a clock edge, so they cannot "sample after settling".
2. Trace the glitch. Each time $B$ falls, $F$ dips $1\to 0\to 1$ for $3\text{ns}$ (Cell F). That momentary $0$ hits the clear pin.
3. Consequence. Every cycle the counter is spuriously reset — it never counts past its first step. A logically "correct" circuit that fails completely in hardware.
4. Fix. Add the consensus $AC$: with $A=C=1$, $F$ stays $1$, the clear line never dips, the counter counts. This is the parent's mistake "registering the output removes the hazard" laid bare — here there is no register to hide behind.

---

Cell H — The exam twist

1. Minimise algebraically. By the consensus theorem, $AC$ is redundant: $AB+\bar{B}C+AC=AB+\bar{B}C$. Why? Consensus terms are always logically implied by the others — that is the definition of redundancy (see Consensus Theorem and Redundancy).
2. Spot the trap. Why this step? Removing $AC$ gives the minimum-gate SOP — but it is exactly Cell A's glitchy circuit. Minimising re-introduces the static-1 hazard.
3. Answer both readings.
   • If the question wants minimum cost: $F=AB+\bar{B}C$.
   • If the question wants hazard-free: keep $F=AB+\bar{B}C+AC$ — the "redundant" term is mandatory.

---

Recall

Recall Which cure form goes with which hazard?

Static-1 (SOP) needs a redundant product term; static-0 (POS) needs a redundant sum factor. ::: Product for SOP (stays 1), sum for POS (stays 0).

Recall Does every adjacency glitch?

No. ::: If a single existing term already covers both adjacent cells (Cell C), there is no handoff and no glitch.

Recall Why can't consensus fix a dynamic hazard?

Because ≥3 reconvergent unequal paths need monotonic switching. ::: One extra term can't guarantee the output changes only once; redesign to a hazard-free network instead.

Recall Glitch width formula?

$w=t_{\text{slow path}}-t_{\text{fast path}}$. ::: It shrinks to $0$ as the delays match, but you never rely on that.