3.3.14 · D1Combinational Circuits

Foundations — Hazards (static and dynamic) in combinational logic

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Before you can read the parent note, you must own every piece of notation it throws at you. We build each one from zero: plain words → the picture → why the topic needs it.


0. What is a "combinational circuit" at all?

Picture a set of switches on the left and one lamp on the right, wired through gates. Flip switches → lamp settles to on or off. There is no "remember what it was before." (Contrast this with a memory circuit — see Synchronous vs Asynchronous Circuits.)

The topic needs this because a hazard is a combinational phenomenon: it lives in the wires between input and output, in the moment before settling.

Figure — Hazards (static and dynamic) in combinational logic
Recall Why is "no memory" important for hazards?

Because the wrong value is only transient ::: it disappears once inputs settle; if the circuit had memory it could lock in the glitch, which is a different (worse) problem.


1. The two symbols 0 and 1 — logic levels

Picture a wire as a pipe that is either empty () or full ().

Why the topic needs it: a glitch is described entirely as a sequence of these values in time, like . You cannot describe a hazard without first agreeing that a wire holds exactly one of two values.


2. The gates: AND, OR, NOT — and their symbols

We use three operations. Each is a physical gate (a small circuit) and a symbol in algebra.

Why the topic needs all three: the classic hazard is built precisely from an input feeding an AND directly and also feeding another AND through a NOT. The NOT is the villain — it adds a delay the direct path does not have.

Figure — Hazards (static and dynamic) in combinational logic
Recall Evaluate

at . ::: so .


3. Building a function:

Now stack the symbols. reads: " is if ( AND ) is true, OR if (NOT- AND ) is true."

Picture: each product term is one path of AND-gates that can raise the output to ; the final OR gate collects all the paths.

See Sum of Products and Product of Sums Forms for how any function can be written either way.

Why the topic needs this: static-1 hazards are analysed in SOP (handing off between product terms that make a ); static-0 hazards are analysed in POS (handing off between sum terms that make a ). Same idea, mirror image.


4. Time and delay: the reason hazards exist

Everything above is timeless algebra. Real gates need time.

Picture: send a pulse into a gate; the output copy comes out a little later, shifted right on a time axis. See Propagation Delay and Gate Timing.

Picture two runners starting together, taking routes of different length, meeting again at the finish. For a moment the fast runner has arrived and the slow one hasn't — they disagree.

Why the topic needs it: a hazard is exactly the moment of disagreement between reconvergent paths. No unequal delay ⇒ no hazard. This is the heart of the whole topic.

Figure — Hazards (static and dynamic) in combinational logic
Recall What is the minimum ingredient list for a static hazard?

One input that changes, reaching the output by two reconvergent paths of different delay ::: (classically, direct vs. through an inverter).


5. The timing diagram: reading

Picture a heartbeat trace: flat at "high", drops to "low", back to "high". The notation is just the sequence of heights the output line takes — a dip.

Why the topic needs it: the entire classification (static-1, static-0, dynamic) is defined by counting transitions in time, so you must be fluent reading these height-sequences.


6. The Karnaugh map & prime implicants — seeing the handoff

Picture a small grid of boxes; stepping one box left/right/up flips a single input from to or back. See Karnaugh Maps and Prime Implicants.

Why the topic needs it: a static-1 hazard shows up visually as two adjacent 1-cells sitting in two different circles — moving between them is a "handoff" from one product term to another, and during the handoff both can drop to .

Picture: a third circle drawn over the gap between the two original circles, so there is no bare handoff. See Consensus Theorem and Redundancy. Adding it is the cure: the bridging term holds the output at throughout the change.

Figure — Hazards (static and dynamic) in combinational logic
Recall What is the consensus of

and ? ::: the variable (true in , complemented in ) is dropped, leaving the shared partners and .


7. Why "registering" doesn't erase the problem

But in asynchronous logic, latch enables, or combinational feedback, the glitch is read whenever it happens and can cause real failure. See Synchronous vs Asynchronous Circuits and Metastability and Setup-Hold Time.


How these foundations feed the topic

Logic levels 0 and 1

Gates AND OR NOT

Functions SOP and POS

Propagation delay

Reconvergent paths

Timing diagram sequences

Hazard types static-1 static-0 dynamic

Karnaugh map and prime implicants

Consensus redundancy term

Hazards in combinational logic

Sync vs Async

The left branch (levels → gates → functions) gives you what the circuit computes. The middle branch (delay → reconvergent paths → timing) gives you why glitches appear in time. The right branch (K-map → consensus) gives you the cure. All three meet at the parent topic.

Return to the parent: Hazards — main note.


Equipment checklist

Read each question; only continue to the parent note if you can answer it out loud.

What does mean and how does it differ from ?
is AND (output 1 only if both are 1); is OR (output 1 if at least one is 1). is NOT arithmetic addition.
What does the overbar in do, and which gate produces it?
It flips the value (NOT); an inverter gate produces it, and that gate adds delay.
Evaluate at .
.
What is propagation delay?
The short time a gate takes to update its output after an input changes.
What are reconvergent paths?
Two or more routes from the same input to the same output through different gates, arriving with different delays.
Write the height-sequence of a static-1 hazard.
(a momentary dip).
Write the height-sequence of a static-0 hazard.
(a momentary spike).
What does a dynamic hazard's sequence look like?
(or more) — three or more transitions where one was expected.
On a K-map, what is a prime implicant?
The largest rectangle of adjacent 1-cells you can circle; each is one SOP product term.
What visual pattern signals a static-1 hazard on a K-map?
Two adjacent 1-cells covered by different prime implicants with no single implicant covering both.
What is the consensus of and , and why add it?
; it bridges the two 1-cells so the output is never dropped during the handoff.
Why can't Boolean simplification remove a hazard?
The consensus term is redundant at steady state but essential during the transition; removing it reintroduces the glitch.