Hazards (static and dynamic) in combinational logic: Visual walkthrough

Before we start, three plain words we will use constantly:

We only need three kinds of gate:

Step 1 — Draw the function as real wires and gates

WHAT. We take the formula $F = A B + \overset{ˉ}{B} C$ and turn it into an actual circuit made of the three gates above.

WHY. A formula pretends everything happens at once. A drawing forces us to see the separate paths a signal takes — and paths are where delays hide. We cannot talk about "unequal delays" until we can point at the two roads.

PICTURE. Look at the figure. Read it left to right:

Inputs $A$ , $B$ , $C$ enter on the left.
$B$ splits: one copy goes straight up into the top AND gate; another copy dives into the inverter (the triangle with a bubble) to become $\overset{ˉ}{B}$ .
The top AND computes $A \cdot B$ — call its output the term $A B$ (blue wire).
The bottom AND computes $\overset{ˉ}{B} \cdot C$ — call its output the term $\overset{ˉ}{B} C$ (yellow wire).
The final OR combines them: $F = A B + \overset{ˉ}{B} C$ .

$F = blue term, direct B A \cdot B + yellow term, B via inverter \overset{ˉ}{B} \cdot C$

Figure — Hazards (static and dynamic) in combinational logic

Step 2 — Freeze the "before" picture: $A = 1, C = 1, B = 1$

WHAT. We hold $A$ and $C$ high forever and set $B = 1$ to start. We read off every wire.

WHY. A hazard only counts if the output is supposed to be the same before and after (see the [!definition] of static hazard in the parent). So we must nail down the starting value first, then the ending value in Step 3, and check they match.

PICTURE. With $B = 1$ :

$\overset{ˉ}{B} = 0, A B = (1) (1) = 1, \overset{ˉ}{B} C = (0) (1) = 0, F = 1 + 0 = 1$

Term-by-term on the drawing:

$\overset{ˉ}{B} = 0$ — the inverter's output is low (yellow wire dark).
$A B = 1$ — top AND is high (blue wire lit): this is what holds $F$ up.
$\overset{ˉ}{B} C = 0$ — bottom AND is low.
$F = 1$ — the OR sees one high input, so it lights.

The output is currently held up entirely by the blue term $A B$ . The yellow term contributes nothing. Keep your eye on who is "holding the output" — that is about to change hands.

Step 3 — Freeze the "after" picture: $A = 1, C = 1, B = 0$

WHAT. Same held inputs, but now $B = 0$ . Read every wire again.

WHY. To confirm this is a genuine static-1 situation: the final value must also be $1$ . If it were $0$ we'd have an ordinary transition, not a hazard.

PICTURE. With $B = 0$ :

$\overset{ˉ}{B} = 1, A B = (1) (0) = 0, \overset{ˉ}{B} C = (1) (1) = 1, F = 0 + 1 = 1$

$\overset{ˉ}{B} = 1$ — inverter output now high (yellow wire lit).
$A B = 0$ — top AND low (blue wire dark) because $B$ went to $0$ .
$\overset{ˉ}{B} C = 1$ — bottom AND now high: this is what holds $F$ up.
$F = 1$ again.

Step 4 — The slow-motion handoff: catch the glitch

WHAT. We zoom into the instant $B$ falls $1 \to 0$ and play it in slow motion, tracking $\overset{ˉ}{B}$ , $A B$ , $\overset{ˉ}{B} C$ , and $F$ on a timeline.

WHY. This is the heart of the derivation. The two roads have different lengths, so the two terms don't switch at the same moment. We must see the gap.

PICTURE — read the timeline top to bottom:

At time $t_{0}$ , $B$ starts falling. Two things now race:

Blue drops fast. $A B$ feeds off $B$ directly (Road 1). The moment $B$ hits $0$ , one AND-delay later $A B \to 0$ .
Yellow rises late. $\overset{ˉ}{B} C$ needs $\overset{ˉ}{B}$ , which comes out of the inverter (Road 2). The inverter must first flip $0 \to 1$ , then the AND reacts. So $\overset{ˉ}{B} C \to 1$ arrives one extra gate-delay later.

Between those two events lies the bad window (shaded red on the figure):

$already dropped A B = 0 AND not risen yet \overset{ˉ}{B} C = 0 ⟹ F = 0 + 0 = 0$

For that one inverter-delay, both terms are 0 at the same time — nobody is holding the output up — so $F$ dips to $0$ . Then $\overset{ˉ}{B} C$ finally rises, $F$ climbs back to $1$ .

$F : 1 ⟶ glitch! 0 ⟶ 1$

That $1 \to 0 \to 1$ is the static-1 hazard.

Step 5 — WHY the K-map warned us in advance

WHAT. We plot $F = A B + \overset{ˉ}{B} C$ on a Karnaugh map and mark the two cells involved in our transition.

WHY. The timeline showed the glitch happens; the map shows why it was inevitable and how to design it away. A K-map is just a grid where physically adjacent cells differ by one input bit — so a single input change = a step to a neighbouring cell. (See Karnaugh Maps and Prime Implicants.)

PICTURE. The map has rows/columns for $A, B, C$ . Two cells matter, both with $A = 1, C = 1$ :

Cell $A = 1, B = 1, C = 1$ → covered by the blue loop $A B$ .
Cell $A = 1, B = 0, C = 1$ → covered by the yellow loop $\overset{ˉ}{B} C$ .

These two cells are adjacent (only $B$ differs — exactly our transition). But they sit in two different loops, and no single loop covers both. On the map, moving between them means stepping out of the blue loop and into the yellow loop — a handoff. That handoff is the same handoff we watched glitch in Step 4.

$adjacent 1-cells in different prime implicants \equiv a hazard-prone handoff$

Step 6 — The cure: bridge the gap with a redundant loop

WHAT. We add one more loop to the map — one that covers both cells at once — and translate it back into an extra AND gate.

WHY. If a single term already covers both cells, there is no handoff: while blue drops and yellow rises, this bridging term stays high the whole time and never lets go of the output. We need the term that spans $A = 1, C = 1$ regardless of $B$ — that is exactly the consensus term. (See Consensus Theorem and Redundancy.)

PICTURE — the bridging loop. Draw a green loop covering both $A = 1, C = 1$ cells (both values of $B$ ). That loop drops $B$ entirely:

$Consensus (A B, \overset{ˉ}{B} C) = true in A B A \cdot true in \overset{ˉ}{B} C C = A C (the variable B, true in one and complemented in the other, is dropped)$

New hazard-free cover:

$F = A B + \overset{ˉ}{B} C + green bridge, holds F = 1 through the whole change A C$

Now replay Step 4 with $A = C = 1$ : the green term $A C = (1) (1) = 1$ stays $1$ the entire time, independent of $B$ . So even in the bad window when blue and yellow are both $0$ , the OR still sees the green $1$ :

$F = A B 0 + \overset{ˉ}{B} C 0 + A C 1 = 1 ✓ no dip$

Step 7 — The degenerate cases (so you never hit an unshown scenario)

WHAT. We check the corners where the hazard cannot fire, so you know the danger is specific.

WHY. The glitch only appears under exact conditions. Knowing when it can't happen is as important as knowing when it can — otherwise you'll fear glitches everywhere.

PICTURE — a small case table:

Held inputs	$B$ change	Blue $A B$	Yellow $\overset{ˉ}{B} C$	Bad window?
$A = 1, C = 1$	$1 \to 0$	drops early	rises late	YES — glitch
$A = 1, C = 0$	$1 \to 0$	drops early	stays $0$ ( $C = 0$ )	No — yellow never rises
$A = 0, C = 1$	$1 \to 0$	stays $0$ ( $A = 0$ )	rises late	No — blue was never $1$
$A = 0, C = 0$	$1 \to 0$	$0$	$0$	No — $F = 0$ throughout, ordinary

Only the first row has both a term that falls and a term that must rise to replace it — the two conditions for a handoff. Everywhere else, one of the terms is pinned by $A = 0$ or $C = 0$ , so there is nothing to hand off. This is exactly why the consensus is $A C$ : the hazard lives precisely where both $A$ and $C$ are $1$ .

The one-picture summary

WHAT. One figure compressing the whole story: the two-road circuit, the glitchy timeline, the K-map handoff, and the green bridge that fixes it — side by side.

Recall Feynman retelling — say it in plain words

A wire called $B$ has to reach the output by two roads. One road is short (straight into an AND). The other goes through an inverter, so it's one step longer. When $B$ drops, the short road's answer collapses right away, but the long road's replacement answer hasn't arrived yet. For that tiny gap, both roads say "0", and the output — which should have stayed "1" — briefly blinks to "0". That blink is the static-1 hazard.

The K-map explains it visually: the two output-1 squares sit in different rings, and stepping from one ring to the other is the handoff where the output can drop. To fix it, we draw one extra ring that covers both squares at once. In gates, that ring is the term $A C$ : whenever $A$ and $C$ are both 1, $A C$ is 1 no matter what $B$ does, so it keeps holding the output up straight through the gap. No gap, no blink. The logic value was never wrong at the ends — only the timing in the middle — and one redundant gate patches the timing.

Recall Quick self-check

Why does the glitch only happen when $A = 1$ and $C = 1$ ? ::: Because you need one term ( $A B$ ) that falls and another term ( $\overset{ˉ}{B} C$ ) that rises to replace it. $A B = 1$ needs $A = 1$ ; $\overset{ˉ}{B} C$ can rise only if $C = 1$ . If either is $0$ , one term is pinned and there is no handoff. What single term cures it and why? ::: $A C$ — it covers both adjacent 1-cells (independent of $B$ ), so it holds the OR output high through the entire transition, filling the bad window. Could a Boolean simplifier find this cure by itself? ::: No — $A C$ is logically redundant, so simplification removes it. You must add it deliberately for glitch-free timing.

Related: Sum of Products and Product of Sums Forms · Synchronous vs Asynchronous Circuits · Metastability and Setup-Hold Time · 3.3.14 Hazards (static and dynamic) in combinational logic (Hinglish)