ISA (Instruction Set Architecture) — RISC vs CISC: Foundations

Before you can argue "RISC vs CISC" you must be fluent in a handful of words and one formula. Throughout this page ISA always means Instruction Set Architecture (the agreed list of commands, registers, and rules a CPU promises to obey). The parent note also throws around register, CPI, pipeline, microcode, load/store, and the symbols $I C$ , $T_{cy c l e}$ , $f$ , $T$ . If any of those is fuzzy, the debate is noise. So we build every one of them from nothing, in an order where each brick sits on the last.

0. The machine we are describing

For now, picture the CPU with two kinds of storage beside it: a huge slow wall of numbered boxes we will call memory (formally defined in section 1) and a tiny fast set of boxes on the CPU's own desk we will call registers (formally defined in section 2). Do not worry about the exact definitions yet — sections 1 and 2 build them properly. This page's job is to earn each of those words before we lean on them.

The figure below is the map for the whole page: everything we define later is a label for something you can see in it.

Figure — ISA (Instruction Set Architecture) — RISC vs CISC

Figure 1 — The machine. The cyan box in the middle is the CPU (the worker). The amber boxes drawn inside it are its on-desk fast storage. The white boxes stacked on the right, each carrying a number 0–5, are the far-away numbered boxes. The double-headed white arrow between CPU and the right-hand stack is labelled "slow (many cycles)": reaching the wall costs the CPU many drumbeats. The cyan arrow on the left shows programs (instruction cards) flowing into the CPU.

1. Memory — the wall of numbered boxes

When the parent writes ADD [mem1], [mem2], the square brackets [ ] mean "the contents of the box at this address," not the address itself. Brackets = "look inside the box."

2. Registers — the boxes on the desk

Figure 2 — Distance is speed. On the left, an amber box labelled "register on the desk" is annotated "1 cycle": the CPU can reach it in a single drumbeat. On the right, a white box labelled "memory box across the room" is annotated "many cycles". The cyan double arrow spanning the gap is captioned "the walk that RISC avoids", and the note underneath states that this gap is the reason the load/store rule (section 6) exists.

This single distance difference is the load/store rule. Hold that thought until section 6.

3. Instruction — one command card

4. Clock, cycle, frequency — the CPU's heartbeat

Figure 3 — The clock. A cyan square wave rises and falls; each full up-and-down block is one drumbeat, labelled "tick 1", "tick 2", … along the bottom. The amber double arrow across one block marks a single $T_{cy c l e}$ — "seconds per tick". The caption underneath reads "more ticks per second (higher $f$ ) → shorter $T_{cy c l e}$ ", making the reciprocal relationship visible: squeeze more ticks into a second and each tick gets shorter.

5. CPI and $T$ — cycles per instruction, and total program time

6. Load / Store — the one rule that defines RISC

7. Pipeline — the assembly line

8. Microcode & Microarchitecture — the hidden kitchen

How these foundations feed the topic

Read the map below top-to-bottom, and it retells this whole page in one glance. On the left branch, memory (numbered boxes) and registers (desk boxes) both feed into the load/store rule — because that rule is precisely a statement about which of those two an arithmetic instruction may touch. In the middle, an instruction feeds two things: counted up over a run it becomes the instruction count $I C$ , and timed against the clock cycle it gives CPI. The clock also fixes the clock period $T_{cy c l e}$ . Those three quantities — $I C$ , $C P I$ , $T_{cy c l e}$ — pour into the Iron Law, which produces the total time $T$ . Finally $T$ , the load/store rule, microcode, and the compiler all converge on the one decision this whole topic argues about: RISC vs CISC. So every box below is a prerequisite you now hold.

Equipment checklist

Self-test: cover the right side and answer before revealing.

What does the acronym ISA stand for, and what is it?

Instruction Set Architecture — the fixed list of commands, registers, and rules a CPU promises to obey.

What is the difference between a register and a memory box?

A register is a tiny fast box on the CPU desk (1 cycle); memory is a huge slow wall across the room (many cycles).

What does

I C

count?

The number of instructions actually executed to run one program (not the number of instruction types).

Give the relationship between

f

and

T_{cy c l e}

T_{cy c l e} = 1/ f

— seconds-per-tick is the reciprocal of ticks-per-second.

What does

C P I

measure?

Average clock cycles one instruction takes to complete.

What does

T

represent in the Iron Law?

The total execution time of one whole program, in seconds — the thing we are ultimately trying to make small.

State the Iron Law and what each factor means.

T = I C \times C P I \times T_{cy c l e}

: instruction count × cycles per instruction × seconds per cycle = seconds per program.

What is the load/store rule?

Arithmetic instructions may operate only on registers; you must Load memory into a register first and Store the result back.

Why do RISC's simple instructions pipeline well?

An assembly line runs smoothly only when every item is the same shape/time; fixed-length simple instructions are identical widgets, so

C P I

approaches 1.

What is microcode?

A tiny built-in program of smaller steps that a CISC chip runs internally to carry out one fat instruction.

ISA vs microarchitecture in one line?

ISA = the visible menu (instruction contract); microarchitecture = the hidden kitchen (physical implementation).