Worked examples — ISA (Instruction Set Architecture) — RISC vs CISC

This page is a drill. The parent note (ISA — RISC vs CISC) built the ideas; here we hammer every case class until none can surprise you in an exam. We lean on one master tool the parent already earned — the Iron Law:

Recall Unit refresher (so no symbol sneaks in undefined)

$1\text{ ns}=10^{-9}$ s (a nanosecond, one-billionth of a second). $1\text{ GHz}=10^9$ ticks per second. These are the only units on this page.

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The scenario matrix

Every problem this topic can throw is one of these cells. The examples below are labelled with the cell they cover, and together they hit all of them.

Cell	What varies	Example that covers it
A. Baseline compare	Both machines fully specified, no equal factors	Ex 1
B. Tie / degenerate	One factor equal → does it cancel?	Ex 2
C. Zero / limiting	A knob → 0 or → ∞ ($CPI\to 1$, ideal pipeline)	Ex 3
D. Sign / direction of change	Speedup vs slowdown — which way does the arrow point?	Ex 4
E. Solve for the unknown knob	Given $T$ and two knobs, back out the third	Ex 5
F. Load/store translation	Count instructions from CISC vs RISC code	Ex 6
G. Real-world word problem	Frequency in GHz, code in a loop, phones vs servers	Ex 7
H. Exam twist / trap	"RISC always wins?" steel-man, hidden equal-CPI case	Ex 8

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Ex 1 — Cell A: full baseline compare

Step 1 — Compute CISC time. Why this step? Multiply all three knobs; the units cancel to seconds. $T_{CISC}=10\times 4\times 0.5=20\text{ns}$

Step 2 — Compute RISC time. Why this step? Same law, same units, so the two are directly comparable. $T_{RISC}=25\times 1.1\times 0.4=11\text{ns}$

Step 3 — Compare. Why this step? Smaller $T$ = faster program. $11<20\Rightarrow \text{RISC wins.}$

Verify: Speedup $=20/11\approx 1.82\times$. Units: $\text{instr}\times \frac{\text{cyc}}{\text{instr}}\times \frac{\text{s}}{\text{cyc}}=\text{s}$. ✔

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Ex 2 — Cell B: one factor is equal (does it cancel?)

Step 1 — Form the products $IC\times CPI$ only. Why this step? Any factor equal on both sides cancels when we take the ratio — computing it is wasted effort for deciding the winner (but we keep it for the final time). $\text{CISC: }12\times 3=36\text{cyc},\text{RISC: }20\times 1.5=30\text{cyc}$

Step 2 — Multiply the shared $T_{cycle}$ back in. Why this step? To report actual times. $T_{CISC}=36\times 0.5=18\text{ns},T_{RISC}=30\times 0.5=15\text{ns}$

Verify: $15=30\times 0.5$ ✔ and $18=36\times 0.5$ ✔. Ratio $=18/15=1.2\times$, and the clock's $0.5$ ns cancels: $36/30=1.2$. ✔

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Ex 3 — Cell C: the limiting/ideal case ($CPI\to 1$)

Step 1 — Compute the ideal (floor) time. Why this step? Set $CPI$ to its limiting value $1$ — the best a one-instruction-per-cycle pipeline can do. $T_{ideal}=30\times 1\times 0.4=12\text{ns}$

Step 2 — Compute the realistic time. Why this step? Real pipelines stall (cache misses, hazards) so $CPI>1$. $T_{real}=30\times 1.5\times 0.4=18\text{ns}$

Step 3 — Interpret the limit. Why this step? To see what "pushing $CPI$ toward its floor" buys. $\frac{T_{real}}{T_{ideal}}=\frac{18}{12}=1.5$ The realistic machine is $1.5\times$ slower than the theoretical floor — exactly the $CPI$ ratio, since the other knobs are shared. (See Pipelining and CPI and the Iron Law of Performance for why $CPI$ can't drop below 1 on a single-issue machine.)

Verify: $12=30\times 0.4$ ✔; $18/12=1.5$ = $1.5/1$ ✔.

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Ex 4 — Cell D: which direction? speedup or slowdown

Step 1 — Before. Why this step? Establish the baseline time. $T_{before}=40\times 1.2\times 0.5=24\text{ns}$

Step 2 — After. Why this step? Same law with the new knobs. $T_{after}=30\times 2.0\times 0.5=30\text{ns}$

Step 3 — Sign of the change. Why this step? Positive change in $T$ means the "optimization" slowed the machine. $\Delta T=30-24=+6\text{ns}\Rightarrow \text{SLOWER.}$

Verify: $24=40\times 1.2\times 0.5$ ✔; $30=30\times 2.0\times 0.5$ ✔; $\Delta =+6>0$ ✔.

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Ex 5 — Cell E: solve for the missing knob

Step 1 — Write the tie condition. Why this step? "Tie" means equal times; set them equal and treat $T_{cycle}$ as the unknown. $25\times 1.1\times T_{cycle}=20\text{ns}$

Step 2 — Solve. Why this step? Isolate the unknown — pure algebra (divide both sides by $25\times 1.1=27.5$). $T_{cycle}=\frac{20}{27.5}\approx 0.727\text{ns}$

Step 3 — Convert to frequency. Why this step? $f=1/T_{cycle}$; architects quote GHz, not ns. $f=\frac{1}{0.727\text{ns}}=\frac{1}{0.727\times 10^{-9}\text{s}}\approx 1.375\text{GHz}$

Verify: $25\times 1.1\times 0.727\approx 20$ ✔; $1/0.727\approx 1.375$ ✔.

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Ex 6 — Cell F: count instructions from load/store code

Step 1 — Write the CISC version. Why this step? CISC arithmetic reads/writes memory directly, so the whole expression collapses.

ADD  C, A, B     ; C = A + B    (memory operands)
SUB  C, C, D     ; C = C - D

$I{C}_{CISC}=2$.

Step 2 — Write the RISC (load/store) version. Why this step? In load/store, EVERY memory value must be LW-ed into a register first, ALU works register-to-register, then SW back. This is forced by the rule.

LW   r1, A       ; load A
LW   r2, B       ; load B
LW   r3, D       ; load D
ADD  r1, r1, r2  ; r1 = A + B
SUB  r1, r1, r3  ; r1 = (A+B) - D
SW   r1, C       ; store result to C

$I{C}_{RISC}=6$.

Step 3 — Ratio. Why this step? This is the "$IC$ went up" half of every Iron-Law trade. $\frac{I{C}_{RISC}}{I{C}_{CISC}}=\frac{6}{2}=3$

Verify: $I{C}_{CISC}=2$, $I{C}_{RISC}=6$, ratio $3$ ✔.

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Ex 7 — Cell G: real-world word problem (phone loop)

Step 1 — Clock period from frequency. Why this step? The Iron Law needs $T_{cycle}$, but we're given GHz. Invert: $T_{cycle}=1/f$. $T_{cycle}=\frac{1}{2.5\times 10^9{\text{s}}^{-1}}=0.4\times 10^{-9}\text{s}=0.4\text{ns}$

Step 2 — Time for one iteration. Why this step? Iron Law with the per-iteration instruction count. $T_{iter}=18\times 1.3\times 0.4\text{ns}=9.36\text{ns}$

Step 3 — Total time for a million iterations. Why this step? Total $IC$ = per-iteration $IC$ × iteration count; equivalently multiply the per-iteration time. $T_{total}=9.36\text{ns}\times 10^6=9.36\times 10^6\text{ns}=9.36\text{ms}$

Verify: $9.36\text{ns}\times 10^6=9.36\times 10^{-3}$ s $=9.36$ ms ✔. Forecast "milliseconds" confirmed. (Caches and Memory Hierarchy would raise the real $CPI$ if the loop misses cache — this is the ideal-cache number.)

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Ex 8 — Cell H: the exam trap ("RISC always wins")

Step 1 — Both times. Why this step? Two knobs equal → they cancel in the ratio, so $IC$ alone decides. $T_{RISC}=30\times 2\times 0.5=30\text{ns},T_{CISC}=18\times 2\times 0.5=18\text{ns}$

Step 2 — Winner. Why this step? Smaller time wins. $18<30\Rightarrow \text{CISC WINS here.}$

Step 3 — Find the RISC $CPI$ that ties. Why this step? To see how much $CPI$ advantage RISC needs to overcome its $IC$ penalty. Set times equal, unknown $CP{I}_R$: $30\times CP{I}_R\times 0.5=18\times 2\times 0.5=18\Rightarrow CP{I}_R=\frac{18}{15}=1.2$

Verify: $T_{RISC}=30$, $T_{CISC}=18$ ✔; tie $CP{I}_R=18/15=1.2$ ✔.

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Recall Self-test (cover the answers)

All three knobs of the Iron Law ::: $T=IC\times CPI\times T_{cycle}$ A machine has equal $T_{cycle}$ and $CPI$ to its rival but 2× the instructions — who wins? ::: The rival (fewer instructions), since only $IC$ differs. Why does load/store RISC emit more instructions for mem+mem? ::: Arithmetic can't touch memory, so each operand needs an explicit LW and the result a SW. $2.5$ GHz clock → period? ::: $1/(2.5\times 10^9)=0.4$ ns. Smallest $CPI$ a single-issue pipeline can reach? ::: $1$ (one instruction finishing per cycle).