Co-packaged optics trends: Visual walkthrough — Hinglish deep dive

6.5.18 · D2 · Hardware › Advanced & Emerging Architectures › Co-packaged optics trends

Step 1 — Bit kya hota hai, aur bandwidth kya hoti hai?

KYA HAI. Ek bit ek yes/no piece of information hota hai: 1 ya 0. Jab ek switch chip bahar ki duniya se baat karta hai, toh woh bits ek ke baad ek wire mein bhejta hai, bahut hi tezi se. Ek second mein jo bits bhej sakta hai, uski count ko bandwidth kehte hain, jo $B$ se likha jaata hai.

KYUN. Yeh poochhhne se pehle ki "chip kitna power jalaata hai?", hume ek clean count chahiye ki woh kitna kaam kar raha hai. Kaam yahan = bits pushed out per second. Toh $B$ haara traffic load ka measure hai.

PICTURE. Figure dekho: chhote squares (bits) ki ek stream chip se nikalkaar wire mein ja rahi hai. Ek second mein, unme se $B$ finish line cross karte hain. Ek modern flagship switch $B = 51.2$ trillion bits har second push karta hai — yahi number hai $51.2 Tb/s$ ( $T = tera = 1 0^{12}$ ).

Step 2 — "Energy per bit," $E_{b}$ kya hota hai?

KYA HAI. Har ek bit ko wire mein dhakele ke liye thodi si energy lagti hai — use charge up karna, copper se drive karna, aur doosre end par clean up karna. Is cost ko energy per bit kehte hain, jo $E_{b}$ se likha jaata hai. Ise picojoules per bit mein measure karte hain, $pJ/bit$ , jahan $1 pJ = 1 0^{- 12}$ joules (joule energy ki everyday unit hai; picojoule ek trillionth hota hai — tiny, lekin aap trillions bits bhejte hain).

KYUN. Power = energy over time, aur total energy = (energy per bit) × (number of bits). Toh agar hame $E_{b}$ aur $B$ pata hai, hum total power predict kar sakte hain. $E_{b}$ woh "price tag" hai jo har bit ke saath chipki hoti hai.

PICTURE. Har marching bit ke saath ab ek chhota coin hai — woh coin $E_{b}$ hai. Ek chhhoti, aasaan wire (right side) sasta coin charge karti hai; ek lambi, mushkil wire (left side) mehnga coin charge karti hai. Message same hai, price alag hai.

Step 3 — Inhe multiply karo: power formula saamne aata hai

KYA HAI. Total electrical-interface power hai $P = cost per bit (pJ/bit) E_{b} \times bits per second (b/s) B$

YEH MULTIPLICATION KYUN, kuch aur kyun nahi? Dekho units kaise cancel hoti hain — yahi poora justification hai: $\frac{joules}{bit} \times \frac{bit}{second} = \frac{joules}{second} = watts .$ "Bit" upar-neeche cancel ho jaata hai, bacha joules per second, aur joules per second exactly watt ki definition hai (watt = har second mein ek joule energy deliver hona). Toh multiply karna guess nahi hai — yeh ek maatra combination hai jiska unit power aata hai.

PICTURE. Ek rectangle: iski width $B$ (bits/s) hai, iski height $E_{b}$ (energy/bit) hai. Rectangle ka area power $P$ hai. Box ko taller banao (mehange bits) ya wider banao (zyada bits) aur area — power — badhta hai.

Physically bada $E_{b}$ aata kahan se hai? Yahi agla step hai — aur puri CPO story ka dil yahi hai. In circuits ke liye SerDes and Wireline Links dekho jo yeh cost pay karte hain.

Step 4 — Lambi, fast wires zyada energy kyun cost karti hain (loss law)

KYA HAI. Ek copper trace signal ko attenuate (kamzor) kar deta hai. Kamzori, decibels (dB — ek loudness-style ratio; zyada dB = zyada signal lost) mein, kuch is tarah badhti hai: $A (dB) \approx loss rate per length α (f) \cdot length L, α (f) = skin effect a f + dielectric b f .$

Har term:

$L$ = woh wire ki length jis par signal travel karta hai.
$f$ = signal frequency (bits kitni fast wiggle karte hain — zyada line rate ⇒ zyada $f$ ).
$α (f)$ = har unit length par kitne dB lose hote hain; yeh frequency ke saath badhta hai.
$a f$ = skin effect — high frequency par current copper ki patli bahari "skin" mein crowd ho jaata hai, resistance $f$ ki tarah badhti hai.
$b f$ = dielectric loss — wire ke aas-paas ka insulator energy ko $f$ ke seedhe proportion mein absorb karta hai.

$f$ KYUN, aur CPO ke liye yeh kyun matter karta hai? Yeh do mechanisms hi woh reasons hain ki faster wire zyada leaky wire hoti hai. Kyunki $A$ $L$ mein linear hai (seedha multiply, koi curve nahi), length ko 100× cut karna dB loss ko 100× cut karta hai. Yahi geometric lever hai jo CPO pull karta hai: $L$ ko ~15 cm se ~2 mm tak chhota karo.

PICTURE. Do panels. Left: ek bar chart jisme $α$ frequency badhne ke saath grow karta hai (28→112→224 Gb/s). Right: ek signal jo tall shuru hota hai aur travel karte karte shrink hota hai — ek lamba faceplate trace end mein barely-visible wiggle ban jaata hai; ek millimeter CPO trace almost full height par rehta hai.

Step 5 — Loss ko $E_{b}$ mein convert karo: bada loss kyun expensive bits banata hai

KYA HAI. Doosre end par ek kamzor, garbled signal ko equalizers (CTLE, DFE, FFE) se rebuild karna padta hai aur re-clock karna padta hai. Jitne zyada dB lose hue, utna hard yeh circuits kaam karti hain, aur jyada hard kaam karne wali circuits zyada energy jalati hain — toh $E_{b}$ recovered dB ke saath badhta hai.

KYUN. Yeh Step 4 ke loss aur Step 2 ke cost ke beech ka bridge hai. Loss ek signal-integrity fact hai; $E_{b}$ ek power fact hai. Equalizer woh machine hai jo "maine 30 dB lose kiya" ko "maine ise fix karne mein 5 pJ/bit spend kiya" mein convert karta hai.

PICTURE. Ek ramp: horizontal axis channel loss (dB) hai, vertical axis $E_{b}$ (pJ/bit) hai. Ek faceplate link ramp par upar hota hai (~5 pJ/bit); ek CPO link neeche-left mein hota hai ~1 pJ/bit ke paas. Arrow jo "shorten $L$ " label kiya hai woh aapko ramp se neeche slide karta hai.

Step 6 — Numbers plug in karo: 256 W faceplate switch

KYA HAI. $P = E_{b} \times B$ use karo faceplate $E_{b} = 5 pJ/bit$ aur $B = 51.2 Tb/s$ ke saath: $P = J/bit 5 \times 1 0^{- 12} \times bit/s 51.2 \times 1 0^{12} = 5 \times 51.2 = 256 W .$

EXPONENTS KYUN CANCEL HOTE HAIN. $1 0^{- 12}$ (pico) times $1 0^{12}$ (tera) = $1 0^{0} = 1$ — yeh perfectly annihilate ho jaate hain. Toh answer sirf $5 \times 51.2$ hai. Yeh sirf electrical I/O hai, switch core ki apni power ke upar se. 256 W ek space-heater ki worth ka power hai jo sirf bits ko faceplate tak pahunchane mein kharch hota hai.

PICTURE. Step-3 rectangle faceplate case ke liye scale par drawn: tall box (5 pJ/bit) × wide (51.2 Tb/s) → ek bada red area jis par 256 W likha hai.

Step 7 — Ab wire chhoti karo: 51.2 W CPO switch

KYA HAI. Same bandwidth, lekin co-packaging $E_{b}$ ko $1 pJ/bit$ par le aata hai: $P = J/bit 1 \times 1 0^{- 12} \times bit/s 51.2 \times 1 0^{12} = 1 \times 51.2 = 51.2 W .$

KYUN. Sirf $E_{b}$ badla — $B$ (traffic) identical hai. Yeh akele reach ke effect ko isolate karta hai. Saving hai $256 - 51.2 = 204.8 W$ , yani $204.8/256 = 80%$ is idealized SerDes-reach portion ka.

PICTURE. Do rectangles side by side: tall red 256 W box aur chhhota mint 51.2 W box, same width, aur upar ka shaved-off region "≈ 200 W saved" shade kiya hua.

Step 8 — Edge cases (reader ko koi unshown scenario nahi dikhna chahiye)

KYA AUR KYUN — formula ke chaar corners:

$B \to 0$ (idle switch). $P = E_{b} \times 0 = 0$ . Koi traffic nahi, koi I/O power nahi — formula gracefully zero ho jaata hai. Achha sanity check hai.
$L \to 0$ (monolithic/optical I/O, "Future" row). Loss $A = α \cdot 0 = 0$ dB, toh equalization → minimal, $E_{b}$ → uska irreducible floor (literally zero nahi: aap abhi bhi drivers, modulators, lasers ke liye pay karte hain). Isliye perfect co-packaging bhi 0 pJ/bit nahi reach kar sakta.
$B$ doubles (12.8 → 25.6 → 51.2 → 102.4 Tb/s). Agar $E_{b}$ fixed rehta, $P$ sirf double hota. Lekin faster lanes $f$ upar push karti hain, toh $α (f)$ badhta hai, toh $E_{b}$ bhi badhta hai — $P$ super-linearly badhta hai. Woh compounding hi asli crisis hai, aur reason hai ki CPO pressure har generation mein badhta rehta hai.
Bahut zyada $E_{b}$ (224 Gb/s copper faceplate par). Jab $L$ lamba rehta hai lekin $f$ soar karta hai, $A$ equalizer ke recoverable budget se zyada ho jaata hai — link sirf power waste nahi karta, kaam karna hi band kar deta hai. Yahi woh hard wall hai jiske upar jump karne ke liye CPO exist karta hai.

PICTURE. Chaar mini-panels: (a) idle → 0 W; (b) $L \to 0$ ek $E_{b}$ floor hit karta hua; (c) $P$ vs $B$ ka super-linear curve "agar $E_{b}$ fixed hota" wali straight line ke upar arc karta hua; (d) ek red "copper cliff" jahan loss recoverable budget se zyada ho jaata hai.

Ek-picture summary

KYA HAI. Ek diagram poori derivation compress karta hai: length → loss → equalization → $E_{b}$ → $P = E_{b} B$ → 256 W vs 51.2 W boxes. Arrows follow karo upar se neeche, aur aapne parent note ka central result "bit" ki definition se re-derive kar liya.

Recall Feynman: poora walkthrough simple words mein

Ek chip bits bhejta hai — chhote yes/no messages — ek wire se, trillions per second; woh count $B$ hai. Har bit ko cross karne mein thodi si energy lagti hai, $E_{b}$ , bas itna. Pinch ko count se multiply karo aur watts milte hain, kyunki units force karti hain: energy-per-bit times bits-per-second energy-per-second hota hai, jo hi ek watt hai.

Ab, pinch badi kyun hoti hai? Kyunki copper wires signal leak karti hain, aur jitni lambi aur fast hoti hain, utna zyada leak karti hain. Doosre end par ek kamzor signal ko clever (power-hungry) circuits se rebuild karna padta hai — toh lambi wires har bit ko expensive banati hain. Ek 51.2 Tb/s switch apne faceplate tak chilla-chilla kar bhejta hua lagbhag 5 pJ per bit pay karta hai aur sirf I/O par 256 watts jalaata hai. Optics ko chip ke bilkul paas le aao toh wire millimeters ki ho jaati hai, leak almost khatam ho jaati hai, rebuild circuits relax ho jaati hain, pinch ~1 pJ par aa jaati hai, aur power ~51 watts par aa jaati hai. Woh 80% cut reach slice hai; baaki sab count karo toh honest whole-link win 30–50% hai. Aur aap kabhi zero nahi hit kar sakte, kyunki lasers, modulators aur drivers hamesha kuch na kuch cost karte hain.

Recall Quick self-test

5 pJ/bit aur 51.2 Tb/s par faceplate power? ::: $5 \times 1 0^{- 12} \times 51.2 \times 1 0^{12} = 256$ W. $E_{b}$ ko $B$ se multiply kyun karte hain? ::: Units: (J/bit)(bit/s) = J/s = watts. Short reach $E_{b}$ kyun cut karta hai? ::: Loss $A = α L$ length mein linear hai; kam loss ⇒ kam equalization ⇒ kam energy/bit. $E_{b}$ 0 kyun nahi ho sakta even at $L = 0$ ? ::: Drivers, modulators, TIAs aur laser inefficiency ek non-zero floor set karte hain.

Related: Silicon Photonics · 2.5D and 3D Packaging · Switch ASIC Bandwidth Scaling · Thermal Management in Packages · Pluggable Optical Modules (QSFP-DD, OSFP) · Data Center Network Topologies