Voltage droop and decoupling capacitors: Exercises

6.4.9 · D4 · Hardware › Power, Thermal & Reliability › Voltage droop and decoupling capacitors

Yeh page ek self-testing ladder hai. Har problem ko solution kholne se pehle khud solve karo. Yahan use kiye gaye har symbol ko parent note Voltage droop and decoupling capacitors mein build kiya gaya hai — agar koi tool samajh nahi aa raha, toh in prerequisites ko revisit karo: Power Delivery Network (PDN), Parasitic inductance and ESL/ESR, di-dt and simultaneous switching noise, Clock timing margin and Vmin, LC resonance and impedance, Dynamic voltage and frequency scaling (DVFS).

Units ki cheat-sheet jis par tum rely karoge:

Level 1 — Recognition

(Kya tum sahi equation pick kar ke problem se numbers read kar sakte ho?)

Exercise 1.1

Ek power wire mein inductance $L = 150 pH$ hai. Core current $0$ se $30 A$ tak $Δ t = 0.5 ns$ mein rise karti hai. Us wire ke across kaun sa transient voltage $V_{L}$ appear hoga?

Recall Solution 1.1

Kaun sa tool aur kyun: changing current se droop ke liye inductor law $V_{L} = L d i / d t$ lagta hai — resistor law $I R$ steady-current question ka answer deta, lekin yahan kuch bhi steady nahi hai; current slew kar rahi hai. Pehle slew rate compute karo: $\frac{d i}{d t} = \frac{30 A}{0.5 \times 1 0 ^{- 9} s} = 6 \times 1 0^{10} A/s$ Phir voltage: $V_{L} = L \frac{d i}{d t} = 150 \times 1 0^{- 12} \times 6 \times 1 0^{10} = 9 V$ Ek "tiny" 150 pH se nine volts ka transient droop — yahi wo villain hai jiske baare mein parent note ne warning di thi.

Exercise 1.2

Ek ceramic capacitor ka $C = 100 nF$ aur parasitic series inductance $E S L = 0.5 nH$ hai. Batao (a) bahut low frequency par kaun sa parameter iska impedance dominate karta hai, aur (b) apni self-resonant frequency se bahut upar kaun sa dominate karta hai.

Recall Solution 1.2

Kaun sa tool aur kyun: cap ka impedance $Z_{c a p} = E S R + j ω E S L + \frac{1}{j ω C}$ hai. Har term alag frequency par win karti hai kyunki uske andar $ω$ (frequency) hai.

(a) Low $ω$ : $\frac{1}{ω C}$ blow up karta hai (denominator mein chota $ω$ ) → capacitive term dominate karti hai. Cap "charge bucket" ki tarah kaam karta hai.
(b) High $ω$ : $ω E S L$ frequency ke saath badhta hai → inductive ( $E S L$ ) term dominate karti hai. Cap "inductor jaisa dikhta hai" aur help karna band kar deta hai. Yahi wajah hai ki ek cap saari frequencies cover nahi kar sakta.

Level 2 — Application

(Formula mein plug karo aur units cleanly carry karo.)

Exercise 2.1

Ek core $Δ I = 25 A$ ka current step leti hai jo $Δ t = 3 ns$ tak rehta hai. Tumhara droop budget $Δ V_{ma x} = 40 mV$ hai. Minimum decoupling capacitance find karo.

Recall Solution 2.1

Kaun sa tool aur kyun: hum chahte hain ki cap charge burst supply kare aur budget se zyada sag na kare. $Δ V = \frac{Δ I Δ t}{C}$ ko $C$ ke liye rearrange karne par sizing box milta hai: $C \geq \frac{Δ I Δ t}{Δ V _{ma x}}$ Charge jo cap deliver kare: $Q = Δ I Δ t = 25 \times 3 \times 1 0^{- 9} = 75 nC$ . Minimum cap: $C \geq \frac{75 \times 1 0 ^{- 9} C}{0.04 V} = 1.875 \times 1 0^{- 6} F = 1.875 μ F$ Toh $\geq 1.875 μ F$ cap is burst ke dauran rail ko 40 mV ke andar rakhta hai.

Exercise 2.2

Ek ceramic cap ka $C = 47 nF$ aur $E S L = 0.8 nH$ hai. Iska self-resonant frequency $f_{0}$ find karo.

Recall Solution 2.2

Kaun sa tool aur kyun: $f_{0}$ woh point hai jahan inductive term $ω E S L$ aur capacitive term $1/ (ω C)$ cancel ho jaate hain — impedance apne minimum ( $= E S R$ ) par dip karta hai. Unhe equal set karne par: $f_{0} = \frac{1}{2 π E S L \cdot C}$ Root ke andar product compute karo: $E S L \cdot C = 0.8 \times 1 0^{- 9} \times 47 \times 1 0^{- 9} = 3.76 \times 1 0^{- 17}$ . $3.76 \times 1 0^{- 17} = 6.13 \times 1 0^{- 9}$ $f_{0} = \frac{1}{2 π \times 6.13 \times 1 0 ^{- 9}} \approx 2.60 \times 1 0^{7} Hz = 26.0 MHz$ ~26 MHz se upar yeh cap inductive ho jaata hai — faster spikes ko tum ek chhote cap ko doge.

Exercise 2.3

Wahi wire jaise pehle thi, $L = 150 pH$ . Ek designer decoupling cap ko trace inductance ke extra $80 pH$ ke baad place karta hai (poor layout). Core $40 A$ ko $1 ns$ mein slew karta hai. Cap ko pin par directly rakhne ke comparison mein, slew ke dauran woh $80 pH$ kitna extra droop create karta hai?

Recall Solution 2.3

Kaun sa tool aur kyun: extra trace sirf cap aur load ke beech aur series $L$ hai; iska droop phir se $V_{L} = L d i / d t$ hai. "Extra" question ke liye sirf added 80 pH matter karta hai. $\frac{d i}{d t} = \frac{40}{1 \times 1 0 ^{- 9}} = 4 \times 1 0^{10} A/s$ $V_{e x t r a} = 80 \times 1 0^{- 12} \times 4 \times 1 0^{10} = 3.2 V$ Cap perfectly sized ho sakta hai, phir bhi distance ka 80 pH 3.2 V droop inject karta hai jo cap fix nahi kar sakta — kyunki extra $L$ cap aur die ke beech hai. Yahi wajah hai ki layout placement hai, sirf value nahi.

Level 3 — Analysis

(Effects combine karo, compare karo, reason karo ki kaun dominate karta hai.)

Exercise 3.1

1.0 V rail par, ek core $Δ I = 50 A$ ko $Δ t = 1 ns$ mein leti hai. Path A: door regulator $L = 500 pH$ wire ke peeche, koi local cap nahi. Path B: ek local cap jo $Δ V_{ma x} = 50 mV$ ke liye sized hai, pin par baitha hai. (a) Bina cap ke inductive droop find karo. (b) Path B ke liye minimum cap find karo. (c) Ek sentence mein explain karo ki cap "jeet jaata hai" kyun, bhale wire unchanged ho.

Recall Solution 3.1

(a) No-cap inductive droop ( $V_{L} = L d i / d t$ ): $\frac{d i}{d t} = \frac{50}{1 \times 1 0 ^{- 9}} = 5 \times 1 0^{10} A/s, V_{L} = 500 \times 1 0^{- 12} \times 5 \times 1 0^{10} = 25 V$ 1 V rail par 25 V droop — chip dead hai. (b) Local cap sizing ( $C \geq Δ I Δ t /Δ V_{ma x}$ ). Pehle convert karo taaki har number base SI ho — amps amps hi rahenge, lekin $Δ t = 1 ns = 1 \times 1 0^{- 9} s$ : $C \geq \frac{Δ I Δ t}{Δ V _{ma x}} = \frac{( 50 A ) \times ( 1 \times 1 0 ^{- 9} s )}{0.05 V} = \frac{50 \times 1 0 ^{- 9} A\cdots}{0.05 V} = 1 \times 1 0^{- 6} F = 1 μ F$ Note karo ki numerator mein units A·s = coulombs hain; volts se divide karne par farads milte hain. Woh unit tag nanoseconds ka $1 0^{- 9}$ bhoolne se bachata hai. (c) Cap kyun jeetta hai: local cap 500 pH se pehle baithta hai, toh 1 ns slew ke dauran fast current cap se bahti hai (low-inductance loop) instead of wire ke through — wire ki current slowly ramp karne milti hai, toh uska $d i / d t$ , aur isliye uska droop, chota rehta hai.

Exercise 3.2

Ek cap ka $C = 10 μ F$ aur $E S L = 2 nH$ hai. Doosre cap ka $C = 1 nF$ aur $E S L = 0.3 nH$ hai. Dono self-resonant frequencies compute karo aur batao ki 200 MHz switching event ke liye tum kaun sa cap rely karoge, aur kyun.

Recall Solution 3.2

Big cap $f_{0}$ : $f_{0, big} = \frac{1}{2 π 2 \times 1 0 ^{- 9} \cdot 10 \times 1 0 ^{- 6}} = \frac{1}{2 π 2 \times 1 0 ^{- 14}} \approx 1.13 MHz$ Small cap $f_{0}$ : $f_{0, small} = \frac{1}{2 π 0.3 \times 1 0 ^{- 9} \cdot 1 \times 1 0 ^{- 9}} = \frac{1}{2 π 3 \times 1 0 ^{- 19}} \approx 290.6 MHz$ 200 MHz ke liye choice: big cap already inductive hai ( $200 MHz ≫ 1.13 MHz$ ) — useless. Small cap ~291 MHz par resonate karta hai, toh 200 MHz par woh apne $f_{0}$ se neeche hai → abhi bhi capacitive → wahi fast event handle karta hai. Yeh hierarchy in action hai: small+close = fast.

Neeche ka figure impedance magnitude $∣ Z ∣$ (vertical, ohms, log scale) dono caps ka frequency (horizontal, hertz, log scale) ke against plot karta hai. Ise aise padho:

Blue V-curve 10 µF big cap hai. Iska lowest point — V ka bottom — apni self-resonant frequency $f_{0, big} \approx 1.13 MHz$ par baitha hai (blue dashed line). Us dip ke left mein curve $1/ (ω C)$ ki tarah girta hai (capacitive); uske right mein $ω E S L$ ki tarah rise karta hai (inductive).
Orange V-curve 1 nF small cap hai; iska dip bahut right mein $f_{0, small} \approx 291 MHz$ par baitha hai (orange dashed line).
Red dotted line 200 MHz event mark karta hai. Notice karo ki yeh blue curve ke rising (inductive) side par land karta hai lekin orange curve ke falling (capacitive) side par — yahi poora answer hai, drawn.

Figure — Voltage droop and decoupling capacitors

Dip zero tak nahi jaata — yeh ek floor par bottom out karta hai. Woh floor cap ka $E S R$ (equivalent series resistance) hai, jise agla exercise concrete banata hai.

Exercise 3.3 — Resonance par $E S R$ kya karta hai

Ek cap ka $C = 47 nF$ , $E S L = 0.8 nH$ , aur $E S R = 15 m Ω$ hai. (a) Apni self-resonant frequency par cap ki impedance magnitude kya hai? (b) Core exactly usi frequency par is cap ke through $6 A$ ripple current pull karta hai. Cap khud kitna droop contribute karta hai, aur kaun se parameter ne use set kiya?

Recall Solution 3.3

Kaun sa tool aur kyun: $f_{0}$ par inductive term $ω E S L$ aur capacitive term $1/ (ω C)$ $Z_{c a p} = E S R + j (ω E S L - 1/ (ω C))$ mein exactly cancel ho jaate hain. Imaginary part zero hai, toh sirf real part bachta hai. (a) Resonance par impedance: $∣ Z_{c a p} (f_{0}) ∣ = E S R = 15 m Ω = 0.015 Ω$ Yeh cap ka minimum hai jo woh kabhi reach karta hai — upar ke figure mein V-curve ka bilkul bottom. (b) Us ripple se droop (Ohm's law, kyunki resonance par cap purely resistive hai): $Δ V = I_{r i ppl e} \times E S R = 6 A \times 0.015 Ω = 0.090 V = 90 mV$ Kaun se parameter ne set kiya: sirf $E S R$ ne. Ek "perfect" $C$ aur tiny $E S L$ bhi impedance ko $E S R$ se neeche nahi push kar sakta, toh resonant valley mein droop ka floor resistance se fix hota hai — yeh real-world edge case hai jo ideal $Δ I Δ t / C$ formula chhupata hai.

Level 4 — Synthesis

(Ground up se multi-step design answer banao.)

Exercise 4.1 — Systematic split ke saath full droop budget

Ek 1.0 V core ka $V_{min} = 0.90 V$ hai, toh total droop budget $Δ V_{b u d g e t} = 100 mV$ hai. Ek burst ke dauran woh $Δ I = 40 A$ ko $Δ t = 2 ns$ ke liye draw karta hai. Local cap aur die ke beech residual loop inductance $L_{l oo p} = 50 pH$ hai. Dono droop terms series mein act karti hain aur simply add hoti hain: $Δ V_{t o t a l} = inductive L_{l oo p} \frac{d i}{d t} + capacitive \frac{Δ I Δ t}{C} \leq Δ V_{b u d g e t}$ (a) Pehle inductive term compute karo (yeh fixed hai — $C$ par depend nahi karta). (b) Inductive term jo kuch chhod jaati hai woh cap ka budget hai — use compute karo. (c) Us remainder ko fit karne ke liye cap size karo.

Recall Solution 4.1

Systematic rule: split arbitrary nahi hai. Inductive term $L_{l oo p} d i / d t$ layout aur slew se fixed hai — isme $C$ nahi hai, toh hum pehle use compute karte hain aur total budget se subtract karte hain. Cap ko sirf jo bachta hai woh milta hai. Yahi method hai. (a) Inductive term ( $d i / d t = 40/2 ns = 2 \times 1 0^{10} A/s$ ): $Δ V_{L} = L_{l oo p} \frac{d i}{d t} = 50 \times 1 0^{- 12} \times 2 \times 1 0^{10} = 1.0 V = 1000 mV$ Reality check: inductive term akela $1000 mV$ hai — pure $100 mV$ budget ka das guna. Cap ke liye koi positive remainder nahi bachta: yeh design infeasible hai as stated. Koi capacitor ise rescue nahi kar sakta, kyunki 2 ns edge se loop inductance already budget blast kar deti hai. (b) Cap ke liye bachta budget: $Δ V_{b u d g e t} - Δ V_{L} = 100 - 1000 = - 900 mV$ — negative, infeasibility confirm karta hai. (c) Algebra jo fix force karta hai: tum pehle inductive term drive down karo. Cap ko ek workable slice dene ke liye — maan lo hum demand karte hain $Δ V_{L} \leq 20 mV$ — required loop inductance ke liye solve karo: $L_{l oo p} \leq \frac{20 \times 1 0 ^{- 3}}{2 \times 1 0 ^{10}} = 1 \times 1 0^{- 12} H = 1 pH$ yaani 50 pH ko $\leq 1 pH$ tak cut karna padega (on-die/on-package placement). Tab cap ko $100 - 20 = 80 mV$ milta hai, aur $C \geq \frac{Δ I Δ t}{80 mV} = \frac{40 \times 2 \times 1 0 ^{- 9}}{0.08} = 1 \times 1 0^{- 6} F = 1 μ F .$ Lesson: budget split physics se decide hota hai — layout-fixed inductive term pehle compute karo; agar woh already budget exceed kar le, toh answer hai "layout fix karo," aur sirf leftover $C$ sizing ke liye jaata hai.

Exercise 4.2 — Two-cap hierarchy coverage

Tumhe PDN impedance $1 MHz$ se $150 MHz$ tak capacitive rakhni hai. Tumhare paas bulk caps ( $C_{1} = 22 μ F$ , $E S L_{1} = 1.5 nH$ ) aur ceramics ( $C_{2} = 22 nF$ , $E S L_{2} = 0.5 nH$ ) hain. Dono $f_{0}$ values compute karke dikhao ki saath mein woh band cover karte hain, aur identify karo ki har ek kis frequency par capacitive rehna band karta hai.

Recall Solution 4.2

Bulk cap: $f_{0, 1} = \frac{1}{2 π 1.5 \times 1 0 ^{- 9} \cdot 22 \times 1 0 ^{- 6}} = \frac{1}{2 π 3.3 \times 1 0 ^{- 14}} \approx 0.876 MHz$ Hmm — $0.876 MHz$ band ke bottom edge 1 MHz se neeche hai, toh bulk cap already band ke shuru mein slightly inductive hai. Practice mein bulk caps low end overlap karte hain; yahan 1 MHz ko effectively unka crossover maano — woh sub-MHz droop carry karte hain aur 1 MHz ke paas hand off karte hain. Ceramic cap: $f_{0, 2} = \frac{1}{2 π 0.5 \times 1 0 ^{- 9} \cdot 22 \times 1 0 ^{- 9}} = \frac{1}{2 π 1.1 \times 1 0 ^{- 17}} \approx 48.0 MHz$ Ceramic ~48 MHz tak capacitive hai. Gap check: ~48 MHz se 150 MHz tak koi bhi cap apne $f_{0}$ se neeche nahi hai — toh yeh pair 150 MHz tak fully cover nahi karta. Tumhe ek teesra, chhota cap chahiye hoga (e.g. sub-nF, on-package) jiska $f_{0} > 150 MHz$ ho. Yeh honest answer hai: do caps high-frequency hole chhod dete hain, proving ki hierarchy mein usually teen tiers hoti hain (bulk / ceramic / on-die).

Level 5 — Mastery

(Wahan reason karo jahan akela algebra mislead kar deta.)

Exercise 5.1 — Capacitance add karna kab help karna band kar deta hai?

Ek designer ek single cap ki value $C$ badhata rehta hai (same package, toh $E S L = 0.5 nH$ fixed) $100 MHz$ noise se ladne ke liye. $f_{0}$ use karke dikhao ki kisi critical $C$ ke baad yeh sirf useless nahi balki counter-productive hai, aur woh $C$ find karo jis par cap ka $f_{0}$ exactly $100 MHz$ par drop karta hai (last value jo abhi bhi wahan capacitive hai).

Recall Solution 5.1

Boundary setup karo: hum chahte hain $f_{0} = 100 MHz$ . Resonance formula ko $C$ ke liye invert karo: $f_{0} = \frac{1}{2 π E S L \cdot C} ⟹ C = \frac{1}{( 2 π f _{0} ) ^{2} E S L}$ Kyun invert, guess nahi: hum exact tipping point ke baare mein pooch rahe hain, toh equation solve karte hain values try karne ki jagah. Step by step compute karo $f_{0} = 100 MHz = 1 \times 1 0^{8} Hz$ aur $E S L = 0.5 nH = 0.5 \times 1 0^{- 9} H$ ke saath: $2 π f_{0} = 2 π \times 1 0^{8} = 6.283 \times 1 0^{8} rad/s$ $(2 π f_{0})^{2} = (6.283 \times 1 0^{8})^{2} = 3.948 \times 1 0^{17}$ $C = \frac{1}{( 2 π f _{0} ) ^{2} E S L} = \frac{1}{3.948 \times 1 0 ^{17} \times 0.5 \times 1 0 ^{- 9}} = \frac{1}{1.974 \times 1 0 ^{8}} \approx 5.07 \times 1 0^{- 9} F \approx 5.07 nF$ Final answer: critical capacitance $C \approx 5.07 nF$ hai. Interpretation: is fixed 0.5 nH package ke saath, ~5.07 nF se bada cap ka $f_{0} < 100 MHz$ hoga, yaani 100 MHz par woh inductive hai. $C$ bada karne se $f_{0}$ neeche push hota hai, iska useful band tumhare target se door ho jaata hai. 5.07 nF ke baad tumhe lower- $E S L$ package ki zaroorat hai $f_{0}$ upar rakhne ke liye — capacitance akela high-frequency response nahi khareed sakta.

Exercise 5.2 — Droop vs. timing margin, end to end

Ek core $1.00 V$ par run karta hai jiska $V_{min} = 0.92 V$ hai. Ek worst-case event $Δ V = Δ I Z_{P D N}$ droop produce karta hai jisme $Δ I = 35 A$ aur effective peak PDN impedance $Z_{P D N} = 2.0 m Ω$ hai. (a) Kya chip survive karta hai? (b) Dynamic voltage and frequency scaling (DVFS) controller rail raise kar sakta hai margin kharidne ke liye — minimum rail voltage kya hai jo droop floor ko $V_{min}$ par rakhe? (c) Ise Clock timing margin and Vmin se ek sentence mein relate karo.

Recall Solution 5.2

Kaun sa tool aur kyun: impedance se droop parent note ki definition hai, $Δ V = Δ I \cdot Z_{P D N}$ — yahan hume effective $Z_{P D N}$ directly diya gaya hai, toh koi $R$ / $L$ split nahi chahiye. (a) Droop compute karo: $Δ V = 35 \times 2.0 \times 1 0^{- 3} = 0.070 V = 70 mV$ Floor voltage $= 1.00 - 0.070 = 0.93 V$ . Kyunki $0.93 V > V_{min} = 0.92 V$ , chip survive karta hai 10 mV spare ke saath. (b) Minimum rail agar floor exactly $V_{min}$ par chahiye: humhe $V_{r ai l} - Δ V \geq V_{min}$ chahiye, toh $V_{r ai l, m i n} = V_{min} + Δ V = 0.92 + 0.070 = 0.99 V$ Toh $0.99 V$ bhi just barely hold karta; $1.00 V$ par run karna 10 mV cushion deta hai. (DVFS rail ko 0.99 V se neeche lower kare toh yeh event $V_{min}$ se neeche dip kar dega.) (c) Timing link: $V_{min}$ se neeche transistors itne slowly switch karte hain ki clock period meet nahi hoti, toh droop directly clock timing margin khaata hai — droop control is timing-margin control.

Connections

Power Delivery Network (PDN)
Parasitic inductance and ESL/ESR
di-dt and simultaneous switching noise
Clock timing margin and Vmin
Dynamic voltage and frequency scaling (DVFS)
LC resonance and impedance