Worked examples — AXI - AMBA on-chip protocols

This is the practice arena for AXI/AMBA On-Chip Protocols. The parent note built the ideas: five channels, the VALID/READY handshake, bursts, and transaction IDs. Here we do the arithmetic — every burst type, every timing edge case, every degenerate input — so no scenario surprises you in an exam or a waveform.

If any symbol below feels unfamiliar, it was defined in the parent. When in doubt, revisit the AXI topic note, or the neighbouring bus architectures note.

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First, the vocabulary (so this page stands alone)

Even though the parent built these, let us re-introduce every symbol we use, so you never have to leave this page.

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The scenario matrix

Before any example, let us enumerate the cases an AXI question can throw at you. Think of this like listing every quadrant before doing trigonometry — we want zero blind spots.

The real question space is $3\times 2\times 2=12$ combinations: three burst types (INCR/WRAP/FIXED) × two handshake-stall sides (slave-slow / master-slow) × two ID relationships (same-ID / different-ID). We deliberately cover every one of the 12 combinations — some examples carry more than one cell so the table stays readable.

Cell	Case class	What makes it tricky	Example(s) that hit it
A	Handshake — slave slower	VALID must hold until READY	Ex 1
B	Handshake — master slower	READY waits, no data lost	Ex 2
C	Burst INCR efficiency	address amortization $T_{addr}/N$	Ex 3
D	Burst WRAP wrap-around	address folds at a boundary	Ex 4
E	Burst FIXED (degenerate)	address never moves ($N$ beats, 1 address)	Ex 5
F	Out-of-order by ID	different IDs reorder, same ID serializes	Ex 6
G	Zero / limiting input	1-beat "burst", $N\to \infty$ limit	Ex 7
H	Real-world word problem	mixed read+write, channel overlap	Ex 8
I	Exam twist	narrow transfer + unaligned start	Ex 9

Filling the full $3\times 2\times 2$ grid. The nine examples above cover the distinct phenomena; the remaining combinations are those same phenomena stacked together. Example 10 closes the grid by explicitly working a stalled handshake happening inside each burst type, with both same-ID and different-ID streams — the cells that a single-topic example does not reach on its own.

Burst type	slave-slow, diff-ID	slave-slow, same-ID	master-slow, diff-ID	master-slow, same-ID
INCR	Ex 3 + Ex 1 pattern	Ex 10 (a)	Ex 3 + Ex 2 pattern	Ex 10 (b)
WRAP	Ex 4 + Ex 1 pattern	Ex 10 (c)	Ex 4 + Ex 2 pattern	Ex 10 (c)
FIXED	Ex 5 + Ex 1 pattern	Ex 10 (d)	Ex 5 + Ex 2 pattern	Ex 10 (d)

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Cell A — Slave slower than master

Forecast: guess the transfer cycle before reading on. (Hint: the handshake rule needs both signals.)

The figure below is a timing diagram: time runs left-to-right in clock cycles, and each horizontal line is one signal — high = logic 1, low = logic 0. The magenta VALID line goes high early and stays high; the violet READY line is late; the orange dashed line marks where they coincide.

Figure 1 — Slave-slower handshake. VALID (magenta) is asserted at cycle 0 and held high; READY (violet) rises only at cycle 3; the orange dashed line marks the transfer where both are 1.

1. Write the handshake rule. Transfer happens when $\text{VALID}=1\wedge \text{READY}=1$ at a rising clock edge. In the figure, that is exactly where the magenta and violet lines are both high.
   • Why this step? This is the only moment a transfer is defined. No coincidence, no transfer.
2. Scan cycle by cycle. Cycle 0–2: VALID=1 but READY=0 → no transfer. Cycle 3: VALID=1, READY=1 → transfer (the orange dashed marker).
   • Why this step? We are literally ANDing the two lines each cycle — read straight off the figure.
3. Apply the hold rule. VALID could not drop during cycles 0–2 (see the magenta line staying flat-high), so the address is still on the wires at cycle 3.
   • Why this step? The AXI spec forbids dropping VALID before the transfer completes — this is what prevents data loss.

Answer: transfer at cycle 3, nothing lost.

Verify: count the stall cycles: transfer cycle $=\max (\text{VALID assert},\text{READY assert})=\max (0,3)=3$. ✓ Units are clock cycles, consistent.

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Cell B — Master slower than slave

Forecast: does READY being early cause the slave to accept undefined data?

Same timing-diagram convention as before, but now the roles are swapped: violet READY is early and held, magenta VALID is late. The orange dashed line again marks the coincidence.

Figure 2 — Master-slower handshake. READY (violet) is high from cycle 0 and held; VALID (magenta) rises at cycle 2; the orange dashed line marks the transfer. Because VALID gates the data, the early READY grabs nothing until cycle 2.

1. Same rule, roles swapped. Transfer needs both = 1. In the figure, READY is already high from cycle 0, so we are waiting on the magenta VALID line.
   • Why this step? The handshake is symmetric — it does not care who is late.
2. Scan. Cycle 0–1: READY=1, VALID=0 → no transfer (master has no valid data yet). Cycle 2: both 1 → transfer.
   • Why this step? Because VALID=0 means "the data on the bus is meaningless," the slave is forbidden from latching it. No garbage.
3. Confirm no loss, no garbage. The single valid beat lands exactly at cycle 2 (orange marker).

Answer: transfer at cycle 2; no garbage grabbed.

Verify: transfer cycle $=\max (2,0)=2$. ✓ Symmetric with Ex 1, as expected.

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Cell C — INCR burst efficiency

Forecast: single-beat costs 8 cycles (parent showed this). Guess the burst cost and the % saved.

1. Single-beat cost. Each transfer = 1 address + 1 data = 2 cycles; four of them = $4\times 2=8$ cycles.
   • Why this step? Baseline. Every transfer re-pays $T_{addr}$.
2. Burst cost. One address (cycle 0) then 4 data beats (cycles 1–4) = $1+4=5$ cycles.
   • Why this step? The slave auto-increments the address internally: $0x1000,0x1004,0x1008,0x100C$. Only ONE address command needed.
3. Compute saving. $\frac{8-5}{8}=0.375=37.5\%$.
   • Why this step? Fraction of cycles eliminated = the payoff of amortizing $T_{addr}$ over $N$ beats.

Answer: 5 cycles vs 8; 37.5% saved.

Verify: general formula ${\text{cycles}}_{\text{burst}}=T_{addr}+N{T}_{data}=1+4=5$. ✓ Matches step 2.

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Cell D — WRAP burst wrap-around

Forecast: INCR would give 0x108, 0x10C, 0x110, 0x114. WRAP is different — guess where it folds.

The figure shows the 16-byte cache line as four boxes; each arrow labelled "beat 0…3" points at the box that beat targets, and the curved navy arrow shows the fold from the top of the line back to its base.

Figure 3 — WRAP burst folding. Four boxes are the 16 bytes of the cache line starting at base 0x100. Coloured arrows show beats 0–3 landing on offsets 8, 12, 0, 4; the curved navy arrow shows the address folding back to the base at the 16-byte boundary.

1. Find the wrap boundary. Wrap length in bytes $=N\times (\text{bytes per beat})=4\times 4=16$ bytes. The aligned region is 0x100–0x10F.
   • Why this step? WRAP is used for cache-line fills: it must stay inside one line, so the boundary equals the burst's byte size.
2. Walk from the start, incrementing by 4. 0x108 → 0x10C (beats 0 and 1 in the figure).
   • Why this step? Same increment as INCR until we hit the top of the region.
3. Wrap at the boundary. Next would be 0x110, which crosses 0x10F. Fold back to the region base: 0x100, then 0x104 (beats 2 and 3, following the curved arrow).
   • Why this step? WRAP wraps the low bits — critical-word-first cache fills need the requested word first, then the rest of the line.

Answer: 0x108, 0x10C, 0x100, 0x104.

Verify: here $\text{base}=\text{0x100}$ (region start) and $\text{start}=\text{0x108}$ (burst start). For beat number $i$ (with $i=0,1,2,3$), address $=\text{base}+((\text{start}-\text{base})+4i)\mathrm{mod}16$. The four beats give offsets $8,12,0,4$ → 0x108,0x10C,0x100,0x104. ✓ All four inside the line.

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Cell E — FIXED burst (degenerate address)

Forecast: what address does beat 3 use?

1. FIXED means no increment. Every beat targets the same address 0x4000.
   • Why this step? A hardware FIFO exposes one register; each read pops a new word but the address never moves. Incrementing would read wrong registers.
2. Addresses: 0x4000, 0x4000, 0x4000, 0x4000.
3. Cycles: still one address + four beats = 5 cycles.
   • Why this step? Burst timing is independent of burst type; only the slave's internal address math differs.

Answer: four identical addresses; 5 cycles.

Verify: offset formula for FIXED = 0 for every beat → all 0x4000. Cycles $=1+4=5$. ✓

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Cell F — Out-of-order by ID

Forecast: which returns first, and when does the second ID=5 read finish?

1. Different IDs may reorder. ID=3 (SRAM, 10-cycle latency) is independent of ID=5 → its data returns at cycle 10.
   • Why this step? AXI allows responses with different IDs in any order — no head-of-line blocking.
2. First ID=5 completes at cycle 100 (its stated 100-cycle DRAM latency, starting at cycle 0).
   • Why this step? Straight latency, nothing blocks it.
3. Second ID=5 must wait for the first ID=5. Same ID ⇒ ordered response. Because the single DRAM port is busy until cycle 100, the second ID=5 read starts at cycle 100 and takes its own 100-cycle latency, completing at $100+100=200$.
   • Why this step? Two effects stack here, and both point the same way: (i) same-ID responses must stay in order, so it cannot return before cycle 100 anyway; (ii) the shared single-port DRAM cannot even begin the second access until the first finishes at cycle 100. Adding the second access's own 100-cycle latency gives cycle 200. This is a clean derivation from the stated latencies — no undefined constants.

Answer: ID=3 at 10, ID=5 (#1) at 100, ID=5 (#2) at 200.

Verify: ordering predicate — ID=3 ≠ ID=5 so it may precede; the two ID=5 completions satisfy $t_{\#1}<t_{\#2}$ ($100<200$), and $t_{\#2}=t_{\#1}+100=200$. ✓

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Cell G — Zero / limiting inputs

Forecast: does a 1-beat burst save anything?

Recall the overhead function we named in the vocabulary. We now derive its formula. A burst pays one address cost $T_{addr}$ (shared across all beats) plus $T_{data}$ per beat. Total cycles $=T_{addr}+N{T}_{data}$; dividing by the $N$ beats gives the cost per transfer: $\text{overhead}(N)=\frac{T_{addr}+N{T}_{data}}{N}=\frac{T_{addr}}{N}+T_{data}$

The figure plots this function against $N$: a magenta curve falling from 2 towards the violet dashed horizontal line at 1, showing the address cost being spread thinner as $N$ grows.

Figure 4 — Overhead per transfer versus burst length N. The magenta curve is overhead(N) = T_addr/N + T_data; it starts at 2 cycles for N=1 (no saving) and falls toward the violet dashed asymptote at 1 cycle as N grows, meaning the single address cost is amortized over more beats.

1. Plug $N=1$. $\text{overhead}(1)=T_{addr}+T_{data}=1+1=2$ cycles.
   • Why this step? A 1-beat burst is just a single transaction — no amortization, so it equals the naive cost. This is the degenerate case where bursts give zero benefit (leftmost point on the curve).
2. Take the limit $N\to \infty$. $\frac{T_{addr}}{N}\to 0$, so $\text{overhead}\to T_{data}=1$ cycle (the violet dashed asymptote).
   • Why this step? The address cost is paid once and spread thinner and thinner. This is the best case — pure data bandwidth.
3. Interpret. Real AXI caps $N$ at 16 (INCR) or 256 (AXI4), so we get close to the limit but never reach it.
   • Why this step? The mathematical limit is an ideal; hardware constraints mean we approach but never touch 1 cycle.

Answer: (a) 1-beat overhead $=2$ cycles; (b) as $N\to \infty$, overhead $\to 1$ cycle.

Verify: $\text{overhead}(1)=\frac{1}{1}+1=2$ ✓, and ${\lim }_{N\to \infty }\left(\frac{1}{N}+1\right)=1$ ✓. Units are clock cycles throughout.

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Cell H — Real-world word problem

Forecast: independent channels — guess whether they block each other.

1. Read path. AR at cycle 0; the DRAM's 15-cycle latency means R data returns at cycle 15.
   • Why this step? The read has nothing to do with the write's channel — it runs on AR/R only.
2. Write path — broken down. The write uses three channels in sequence: AW (address) at cycle 0, W (data) at cycle 1, and B (write response) at cycle 2. Concretely: cycle 0 the address handshake completes; cycle 1 the single data beat handshakes; cycle 2 the cache asserts B to acknowledge the buffered write. That is 2 cycles from address to response.
   • Why this step? We are not asserting "2 cycles" — we are counting one cycle per channel handshake (AW → W → B), which is exactly how a fast buffered write completes.
3. Compare. Write done at 2, read done at 15. The write finished 13 cycles earlier, unblocked.
   • Why this step? Channel independence is the whole point: a fast write is not held hostage by a slow read (see coherence for why write ordering across masters still needs IDs).

Answer: write completes at cycle 2, read at cycle 15; write did not wait.

Verify: write cycles $=1$ (AW) $+1$ (W→B) $=2$; $t_{\text{write}}=2<t_{\text{read}}=15$, gap $=13$. ✓

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Cell I — Exam twist: narrow transfer + unaligned start

Forecast: which of the 4 byte lanes carry valid data in beat 0?

1. Compute addresses. Transfer size = 2 bytes, so INCR steps by 2: 0x1002, 0x1004, 0x1006.
   • Why this step? INCR increments by the transfer size, not the bus width. Narrow transfers step in small strides.
2. Locate the byte lanes for beat 0. The bus's four lanes cover bytes 0x1000–0x1003. Address 0x1002 occupies the lanes for bytes 2 and 3.
   • Why this step? On a 4-byte bus, byte address mod 4 picks the lane. $0x1002\mathrm{mod}4=2$ → lanes 2 and 3.
3. Write the strobe. WSTRB = 1100 (binary): lanes 3 and 2 active, lanes 1 and 0 idle.
   • Why this step? WSTRB is one bit per byte lane marking which lanes carry live data. Unaligned narrow writes light up only the relevant lanes; the rest must be masked or memory corrupts.

Answer: addresses 0x1002, 0x1004, 0x1006; first-beat WSTRB = 0b1100.

Verify: step $=2$, so beats give $0x1002,0x1004,0x1006$. Lane index $=0x1002\mathrm{mod}4=2$; a 2-byte transfer sets lanes 2 and 3 → strobe bits $2^2+2^3=4+8=12=0b1100$. ✓

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Filling the stacked grid cells — handshake stall inside each burst type

Forecast: a one-cycle stall adds how many cycles, and does the burst type change that?

1. Baseline burst cost. From Cell C: a clean 4-beat burst = $T_{addr}+4T_{data}=1+4=5$ cycles.
   • Why this step? We need the no-stall reference before adding the bubble.
2. (a) INCR, one slave stall on beat 2. The stall inserts exactly one bubble cycle (READY low for one cycle), so total $=5+1=6$ cycles. Same-ID vs different-ID does not change this single burst — ID only orders it against other bursts.
   • Why this step? Each inserted wait state is one extra cycle; the handshake rule (transfer only when both high) makes the stall cost exactly its duration.
3. (b) INCR, master-slow stall on beat 2. Symmetric: if the master drops VALID for one cycle instead, the same single bubble appears → $5+1=6$ cycles. It does not matter which side stalls; the cost is the stall duration.
   • Why this step? The handshake is symmetric (Ex 1 vs Ex 2), so slave-slow and master-slow give identical timing for the same stall length.
4. (c) WRAP and (d) FIXED, same stall. Burst type only changes the address sequence (Ex 4, Ex 5), never the timing. So WRAP and FIXED also cost $5+1=6$ cycles with one bubble.
   • Why this step? This is the key unification: timing depends on beats and stalls; addressing depends on burst type. They are independent axes — which is exactly why the $3\times 2\times 2$ grid collapses to a handful of rules.

Answer: every combination = 6 cycles for one inserted stall; burst type and stall-side are timing-irrelevant, ID relationship affects only cross-burst ordering.

Verify: clean burst $=1+4=5$; one stall adds 1 → $6$ for all of (a),(b),(c),(d). ✓

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Recall drills

Recall When does an AXI transfer actually happen?

On a rising clock edge when both VALID and READY are 1. ::: Coincidence of both handshake signals.

Recall 4-beat INCR vs four singles at

$T_{addr}=T_{data}=1$ — cycles and saving? 5 vs 8 cycles ::: 37.5% saved.

Recall 4-beat WRAP from

0x108 in the 0x100 line — the four addresses? 0x108, 0x10C, 0x100, 0x104 ::: it folds back at the 16-byte boundary.

Recall Two reads with the

same ID — can they complete out of order? No ::: same ID forces in-order completion; different IDs may reorder.

Recall A one-cycle stall on any burst type — how many extra cycles?

One ::: burst type and stall-side never change timing, only addressing/ordering.

Related: DMA controllers issue exactly these AXI bursts; ARM cores are the classic masters; contrast with off-chip PCIe which packetizes instead of using side-band handshakes.