Question bank — AXI - AMBA on-chip protocols

True — the channels are physically separate wire bundles with their own VALID/READY pairs, so AW, W, B, AR and R can all handshake on the very same rising edge with no contention.

False — APB is unpipelined and single-transaction; AXI's whole point is independent address/data channels, outstanding transactions and out-of-order completion. Width is the least of the differences.

False — for reads the data is the response: each read data beat on the R channel carries an RRESP status field, so no sixth channel is needed.

False — VALID must stay high until the transfer completes (VALID and READY both high on a rising edge). Dropping it early would deadlock the handshake and violate the protocol.

True — a slave may pre-assert READY while waiting; the transfer simply happens on the cycle when VALID also becomes high. Only VALID has the "hold until transfer" rule, not READY.

False — different IDs may complete in any order (that's the point of IDs). Only transactions sharing the same ID are guaranteed ordered.

True — length (beat count) and size (bytes/beat) determine byte count; INCR vs WRAP only changes which addresses are hit, not how many beats occur.

False — that's exactly its purpose: draining a FIFO/peripheral register (e.g. a UART RX buffer) where each read pops new data from one fixed address.

False — bursts amortize the address cost over many beats; a lone single-beat transfer gets no amortization ($T_{\text{addr}}$ is paid in full). Bursts only win when $N>1$.

Error — no transfer occurs until both VALID and READY are high on the same edge. With READY stuck at 0, nothing transfers; the channel is stalled, not fast.

Error — a $W$-bit ID gives $2^W$ distinct tags, so 3 bits allow $2^3=8$ outstanding, not 3. The count is the number of ID values, not the bit width.

Error — sequentially rising addresses that don't roll over are an INCR burst. WRAP is for when the address must fold back at a boundary (cache-line fills), not for open-ended array scans.

Not necessarily an error, but the claim that it's forbidden is wrong — AXI does not force AW before W; W data may lead, lag, or align with its AW address as long as they share the AWID. (The B response, however, only comes after the write commits.)

Error — AXI is not a single shared time-slot bus. Independent channels plus transaction IDs let the fast DRAM read complete without waiting behind the slow peripheral.

Error — same ID implies a possible dependency (e.g. a pointer write before a payload write). Reordering same-ID transactions could break memory consistency, which is exactly why the spec forbids it.

Because address traffic is tiny compared to data, and decoupling lets a master pipeline: issue address N+1 while data N is still streaming, so address bandwidth and data bandwidth scale independently.

A write's success is only known after the slave commits the buffered data, which happens later than the last W beat — so the acknowledgement must be a separate, later signal. A read's success rides along inside the returning R data.

If VALID could drop while READY was still low, the two sides could keep missing each other or the initiator could abandon a half-offered transfer — a deadlock/loss hazard. Holding VALID guarantees eventual coincidence and forward progress.

Without IDs, responses must return in issue order, so one slow access (DRAM) freezes every later fast one. IDs let each response be matched to its request independently, so a fast SRAM read (different ID) can overtake a stalled DRAM read.

The single address cost $T_{\text{addr}}$ is spread over $N$ beats, giving per-transfer overhead $T_{\text{addr}}/N+T_{\text{data}}$; as $N\to \infty$ the $T_{\text{addr}}/N$ term vanishes and only the unavoidable data time remains.

The VALID/READY coincidence rule is fully local between one master and one slave — each pair negotiates its own transfer, so flow control is distributed and scales to many endpoints (see 6.3.01-bus-architectures-and-topologies for the contrast with arbitrated shared buses).

No — burst length encodes at least one beat (AXI4 length field 0 means one beat, not zero). Every valid transaction transfers at least one data beat, so there is no "empty" transfer.

The one issued first must return first, regardless of speed, because same-ID transactions are ordered. If the slow one was issued first, the fast one waits behind it — the price of same-ID ordering.

0x100, 0x104, 0x108, 0x10C, then it wraps back to 0x100 for continuation. The wrap boundary is aligned to (beats × size), so it folds at the 16-byte block edge rather than running off.

No transfer — the handshake requires the coincidence to be sampled at a rising ACLK edge. AXI is a synchronous protocol; levels between edges don't move data.

It must stall (hold the new VALID low or wait) until an outstanding transaction retires, since only $2^{W_{\text{ID}}}$ tags (here 16) can be in flight; there is no free ID to label the 17th.

No — read and write channels are independent and unordered relative to each other by default. Ordering across the two must be enforced by the master (or coherency logic, see 6.3.04-memory-coherence-protocols), not assumed from AXI alone.