AXI - AMBA on-chip protocols: Exercises — Hardware deep dive

Before we start, one shared picture of the five channels — keep it open in your head for every problem.

Two extra reminders in plain words, because every problem below leans on them:

Level 1 — Recognition

Exercise 1.1 (L1)

Name the five AXI channels and, for each, say who drives VALID (master or slave) and in one phrase what travels on it.

Recall Solution

Channel	Drives VALID	Carries
AW (Write Address)	Master	write address + burst info
W (Write Data)	Master	the data words being written
B (Write Response)	Slave	OKAY / error after write commits
AR (Read Address)	Master	read address + burst info
R (Read Data + Response)	Slave	read data and its response code

The trick: the address and write-data channels flow master→slave, so the master owns VALID there. The response channels flow slave→master (B and R), so the slave owns VALID. Read response is fused into R — that is why there are 5 channels, not 6.

Exercise 1.2 (L1)

For each AXI burst type, match it to its natural hardware use: FIXED, INCR, WRAP. Candidates: (a) filling a cache line, (b) draining a UART receive FIFO, (c) a circular audio buffer.

Recall Solution

FIXED → (b) UART RX FIFO. The address does not change; every beat hits the same register.
INCR → (a) cache line fill. Address climbs by the transfer size each beat: 0x1000, 0x1004, ....
WRAP → (c) circular buffer. Address increments then wraps back to the aligned start when it hits the boundary.

Level 2 — Application

Exercise 2.1 (L2)

On one channel, VALID and READY behave as below (cycle 0 is the first). At which cycle does the transfer happen, and how many transfers total?

Cycle    0   1   2   3   4
VALID    0   1   1   1   0
READY    1   0   1   0   1

Recall Solution

A transfer occurs only when $VALID = 1 \land READY = 1$ on the same rising edge.

Cycle 0: 0,1 → no (sender not ready).
Cycle 1: 1,0 → no (receiver not ready).
Cycle 2: 1,1 → YES. One transfer.
Cycle 3: 1,0 → no.
Cycle 4: 0,1 → no.

Exactly one transfer, at cycle 2. Note VALID legally stayed high from cycle 1→2 while waiting; the spec forbids dropping VALID before the handshake, which is why it did not fall at cycle 2 boundary until the transfer landed.

Exercise 2.2 (L2)

You must move 16 bytes starting at 0x1000, data bus width 4 bytes. Compare cycle counts for (A) four single-beat transactions vs (B) one 4-beat INCR burst, using the simple model "1 cycle per address, 1 cycle per data beat, back-to-back." Then compute the percent cycles saved.

Recall Solution

16 bytes ÷ 4 bytes/beat = 4 beats.

Method A (4 singles): each transaction = 1 address + 1 data = 2 cycles. $4 \times 2 = 8 cycles, 4 address cycles$

Method B (1 burst of 4): 1 address + 4 data. $1 + 4 = 5 cycles, 1 address cycle$

Saved: $\frac{8 - 5}{8} = \frac{3}{8} = 0.375 = 37.5%$

The address cost got amortised over 4 beats instead of paid 4 times.

Exercise 2.3 (L2)

Using the burst formula, if you make the burst 8 beats long (same 4-byte bus, INCR), what is the per-transfer overhead in the model $\frac{T _{addr}}{N} + T_{data}$ with $T_{addr} = T_{data} = 1$ cycle? Compare to $N = 4$ .

Recall Solution

$N = 4 : \frac{1}{4} + 1 = 1.25 cycles/beat$ $N = 8 : \frac{1}{8} + 1 = 1.125 cycles/beat$ Doubling the burst halves the remaining address penalty ( $0.25 \to 0.125$ ). As $N \to \infty$ the overhead approaches the floor $T_{data} = 1$ cycle/beat — you can never beat one cycle per data word.

Level 3 — Analysis

Exercise 3.1 (L3)

A master issues three reads back-to-back:

ID = 5, addr 0x8000, DRAM, latency 100 cycles
ID = 3, addr 0x2000, SRAM, latency 10 cycles
ID = 5, addr 0x8100, DRAM, latency 100 cycles

Assume each latency counts from cycle 0 (all addresses accepted at cycle 0). Give the completion cycle of each and explain the ordering.

Recall Solution

AXI rule: different IDs may complete out of order; same-ID must complete in issue order.

Cycle 10: ID=3 data (0x2000). Different ID, no dependency — returns as soon as SRAM is done.
Cycle 100: ID=5 data (0x8000). First of the two ID=5 reads.
Cycle 110: ID=5 data (0x8100). Its raw latency is 100 (done at cycle 100), but it shares ID=5 with the first, which finishes at cycle 100. Same-ID ordering forces it to wait behind — so its data may only appear on cycle ≥ 101; with one beat/cycle it lands at 110 in the parent's model (serialised after the first ID=5 completes).

Completion order: ID3 (10) → ID5#1 (100) → ID5#2 (110).

Exercise 3.2 (L3)

A master has a 4-bit transaction ID field. What is the maximum number of outstanding transactions it can distinguish, and why does that number, not the number of physical wires, set the concurrency limit?

Recall Solution

$Max outstanding = 2^{W_{ID}} = 2^{4} = 16$ Each in-flight transaction needs a unique tag so a returning response can be matched to its request. With 4 bits you can label 16 distinct tags. It is the number of distinct labels, not the channel wire count, that bounds how many requests can be "in the air" simultaneously — the channels themselves are reused cycle after cycle.

Level 4 — Synthesis

Exercise 4.1 (L4)

Build the full cycle-by-cycle timeline of a single 4-beat INCR write to 0x1000 (4-byte bus). Model: AW accepted at cycle 0; W beats flow one per cycle starting cycle 1 (slave READY always high); the slave asserts B (BVALID) two cycles after the last W beat. When does the write fully complete (B handshake), and how many total cycles from cycle 0?

Recall Solution

Cycle 0: AW handshake — address 0x1000, AWLEN=3 (=4 beats), INCR.
Cycle 1: W beat 0 → 0x1000
Cycle 2: W beat 1 → 0x1004
Cycle 3: W beat 2 → 0x1008
Cycle 4: W beat 3 → 0x100C, this beat carries WLAST=1.
Slave asserts B two cycles after last W beat (cycle 4): cycle 6.
Cycle 6: B handshake, BRESP=OKAY. Write fully complete.

Total = 7 cycles (cycle 0 through cycle 6 inclusive). The B channel is why the master knows the store actually landed — without it, the master could race ahead and read stale data.

Exercise 4.2 (L4)

A WRAP burst of 4 beats, 4-byte transfers, starts at 0x108. The wrap boundary for a 4-beat×4-byte burst is $4 \times 4 = 16$ bytes, aligned to 0x100. List the four addresses in the order they are driven.

Recall Solution

Wrap region = 16 bytes aligned down from the start: 0x100–0x10F. Start at 0x108, step +4, and wrap back to 0x100 when leaving the region: $0 x 108 \to 0 x 10 C \to 0 x 100 \to 0 x 104$ Beat 3 (0x10C) is the top of the region; the next +4 would hit 0x110 which is outside, so it wraps to the aligned base 0x100, then 0x104. This is exactly how a cache line fills critical-word-first: start at the word the CPU stalled on, then wrap to grab the rest of the line.

Level 5 — Mastery

Exercise 5.1 (L5)

Explain, using the handshake rule, why AXI mandates that once VALID is asserted it must stay high until the transfer completes (VALID may not be withdrawn). Construct the deadlock/data-loss scenario that this rule prevents.

Recall Solution

Transfer needs $VALID \land READY$ on one edge. Suppose VALID could drop while waiting. Broken scenario: master raises VALID at cycle 1 (data on wires). Slave is busy, READY=0. At cycle 2 master, impatient, drops VALID and changes the wires. At cycle 2 the slave finally raises READY — but now the sender says "nothing valid here," so the beat is lost, or worse, the slave latches the changed wires as if they were the original beat (data corruption). The "VALID sticks until handshake" rule guarantees the receiver always has a stable, still-offered beat to grab the moment it becomes READY. It converts a fragile timing race into a robust rendezvous. (Note the asymmetry: READY is allowed to drop freely; only the sender's offer must be persistent.)

Exercise 5.2 (L5)

A designer wants to overlap a read from slow DRAM and a write to fast cache from the same master, expecting them to run in parallel. A colleague objects: "they'll serialise — one bus." Who is right, and precisely which architectural feature settles it? Then give the one condition under which a read and a read to the same address could still be forced to order.

Recall Solution

The designer is right. The write uses AW + W + B; the read uses AR + R. These are physically separate channels, so a write address, write data, read address, and read data can all be in flight on the same cycle. There is no single shared data bus to serialise on — that is the entire point of channel separation. The ordering exception: two reads are only forced into order if they carry the same transaction ID (ARID). Same-ID = ordered completion, even to different addresses; different-ID = free to reorder. So parallelism is limited by ID assignment, not by the read/write split.

Recall Self-test recap (cover the right side)

Transfer condition on any channel ::: VALID=1 AND READY=1 on the rising clock edge Number of AXI channels and why not 6 ::: 5 — read data and read response are fused on R Percent cycles saved, 16 B via 4-beat burst vs 4 singles ::: 37.5% Max outstanding with a 4-bit ID ::: 16 (that is 2^4) Same-ID transactions must ::: complete in issue order WRAP addresses from 0x108, 4 beats × 4 B ::: 0x108, 0x10C, 0x100, 0x104 Why VALID cannot be withdrawn ::: to prevent lost/corrupted beats when READY arrives late

Where to go next

Revisit the channel model in the parent topic.
IDs and same-address ordering connect deeply to memory coherence protocols.
Bursts and outstanding transactions matter for DMA controllers moving big blocks.
Compare on-chip AXI to off-chip PCIe architecture and the broader bus architectures and topologies.
AXI is ARM's interconnect — see the ARM architecture overview.
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