AXI - AMBA on-chip protocols: Exercises — Hinglish deep dive

6.3.7 · D4 · Hardware › Interconnects, Buses & SoC › AXI - AMBA on-chip protocols

Shuru karne se pehle, paanch channels ki ek shared picture — har problem ke liye ise apne dimaag mein khula rakho.

Do extra reminders plain words mein, kyunki neeche ki har problem inhi pe tiki hai:

Level 1 — Recognition

Exercise 1.1 (L1)

Paanch AXI channels ke naam batao aur har ek ke liye, kaun VALID drive karta hai (master ya slave) aur ek phrase mein kya travel karta hai usp pe.

Recall Solution

Channel	VALID Drive Karta Hai	Carry Karta Hai
AW (Write Address)	Master	write address + burst info
W (Write Data)	Master	woh data words jo write ho rahe hain
B (Write Response)	Slave	OKAY / error jab write commit ho jaata hai
AR (Read Address)	Master	read address + burst info
R (Read Data + Response)	Slave	read data aur uska response code

Trick yeh hai: address aur write-data channels master→slave flow karte hain, toh master wahan VALID ka owner hai. Response channels slave→master flow karte hain (B aur R), toh slave VALID ka owner hai. Read response R mein fuse ho jaata hai — isliye 5 channels hain, 6 nahi.

Exercise 1.2 (L1)

Har AXI burst type ko uske natural hardware use se match karo: FIXED, INCR, WRAP. Candidates: (a) cache line fill karna, (b) UART receive FIFO drain karna, (c) ek circular audio buffer.

Recall Solution

FIXED → (b) UART RX FIFO. Address change nahi hota; har beat usi register ko hit karta hai.
INCR → (a) cache line fill. Address har beat pe transfer size ke barabar badhta hai: 0x1000, 0x1004, ....
WRAP → (c) circular buffer. Address increment hota hai phir boundary hit karne pe aligned start pe wrap ho jaata hai.

Level 2 — Application

Exercise 2.1 (L2)

Ek channel pe, VALID aur READY neeche diye anusaar behave karte hain (cycle 0 pehla hai). Kis cycle pe transfer hota hai, aur total kitne transfers hote hain?

Cycle    0   1   2   3   4
VALID    0   1   1   1   0
READY    1   0   1   0   1

Recall Solution

Transfer tabhi hota hai jab $VALID = 1 \land READY = 1$ ek hi rising edge pe ho.

Cycle 0: 0,1 → nahi (sender ready nahi).
Cycle 1: 1,0 → nahi (receiver ready nahi).
Cycle 2: 1,1 → HAAN. Ek transfer.
Cycle 3: 1,0 → nahi.
Cycle 4: 0,1 → nahi.

Exactly ek transfer, cycle 2 pe. Note karo VALID legally cycle 1→2 tak high raha wait karte hue; spec forbid karta hai VALID ko handshake se pehle drop karna, isliye woh cycle 2 boundary pe tab tak nahi gira jab tak transfer nahi hua.

Exercise 2.2 (L2)

Tumhe 16 bytes move karne hain 0x1000 se, data bus width 4 bytes hai. (A) chaar single-beat transactions vs (B) ek 4-beat INCR burst ke cycle counts compare karo, simple model use karke "1 cycle per address, 1 cycle per data beat, back-to-back." Phir percent cycles saved calculate karo.

Recall Solution

16 bytes ÷ 4 bytes/beat = 4 beats.

Method A (4 singles): har transaction = 1 address + 1 data = 2 cycles. $4 \times 2 = 8 cycles, 4 address cycles$

Method B (1 burst of 4): 1 address + 4 data. $1 + 4 = 5 cycles, 1 address cycle$

Saved: $\frac{8 - 5}{8} = \frac{3}{8} = 0.375 = 37.5%$

Address cost 4 baar pay karne ki jagah 4 beats pe amortise ho gayi.

Exercise 2.3 (L2)

Burst formula use karte hue, agar burst 8 beats lamba ho (same 4-byte bus, INCR), toh model $\frac{T _{addr}}{N} + T_{data}$ mein per-transfer overhead kya hoga jab $T_{addr} = T_{data} = 1$ cycle ho? $N = 4$ se compare karo.

Recall Solution

$N = 4 : \frac{1}{4} + 1 = 1.25 cycles/beat$ $N = 8 : \frac{1}{8} + 1 = 1.125 cycles/beat$ Burst double karne se remaining address penalty aadhi ho jaati hai ( $0.25 \to 0.125$ ). Jaise jaise $N \to \infty$ , overhead floor $T_{data} = 1$ cycle/beat ke paas pahunchta hai — tum kabhi bhi ek cycle per data word se better nahi ho sakte.

Level 3 — Analysis

Exercise 3.1 (L3)

Ek master teen reads back-to-back issue karta hai:

ID = 5, addr 0x8000, DRAM, latency 100 cycles
ID = 3, addr 0x2000, SRAM, latency 10 cycles
ID = 5, addr 0x8100, DRAM, latency 100 cycles

Maan lo har latency cycle 0 se count hoti hai (saare addresses cycle 0 pe accept ho jaate hain). Har ek ka completion cycle batao aur ordering explain karo.

Recall Solution

AXI rule: alag IDs out of order complete ho sakte hain; same-ID ko issue order mein complete karna hoga.

Cycle 10: ID=3 data (0x2000). Alag ID, koi dependency nahi — jaise hi SRAM done hota hai return ho jaata hai.
Cycle 100: ID=5 data (0x8000). Do ID=5 reads mein se pehla.
Cycle 110: ID=5 data (0x8100). Uski raw latency 100 hai (cycle 100 pe done), lekin woh ID=5 share karta hai pehle ke saath, jo cycle 100 pe finish hota hai. Same-ID ordering ise wait karne ke liye force karti hai — toh uska data ≥ 101 cycle pe hi appear ho sakta hai; ek beat/cycle ke saath woh parent ke model mein 110 pe land karta hai (pehle ID=5 ke complete hone ke baad serialise hoke).

Completion order: ID3 (10) → ID5#1 (100) → ID5#2 (110).

Exercise 3.2 (L3)

Ek master ke paas 4-bit transaction ID field hai. Maximum kitne outstanding transactions woh distinguish kar sakta hai, aur kyun woh number, physical wires ki sankhya nahi, concurrency limit set karta hai?

Recall Solution

$Max outstanding = 2^{W_{ID}} = 2^{4} = 16$ Har in-flight transaction ko ek unique tag chahiye taaki returning response ko uski request se match kiya ja sake. 4 bits ke saath tum 16 distinct tags label kar sakte ho. Yeh distinct labels ki sankhya hai, channel wire count nahi, jo limit karta hai ke kitne requests ek saath "air mein" ho sakte hain — channels khud cycle-by-cycle reuse hote hain.

Level 4 — Synthesis

Exercise 4.1 (L4)

0x1000 pe ek single 4-beat INCR write ka poora cycle-by-cycle timeline banao (4-byte bus). Model: AW cycle 0 pe accept hota hai; W beats cycle 1 se shuru hoke ek per cycle flow karte hain (slave READY hamesha high); slave B (BVALID) assert karta hai last W beat ke do cycles baad. Write fully kab complete hoti hai (B handshake), aur cycle 0 se total kitne cycles?

Recall Solution

Cycle 0: AW handshake — address 0x1000, AWLEN=3 (= 4 beats), INCR.
Cycle 1: W beat 0 → 0x1000
Cycle 2: W beat 1 → 0x1004
Cycle 3: W beat 2 → 0x1008
Cycle 4: W beat 3 → 0x100C, is beat mein WLAST=1 hota hai.
Slave B do cycles baad last W beat (cycle 4) ke: cycle 6.
Cycle 6: B handshake, BRESP=OKAY. Write fully complete.

Total = 7 cycles (cycle 0 se cycle 6 inclusive). B channel isliye hai — taaki master ko pata chale ke store actually land hua — iske bina master aage race kar sakta tha aur stale data read kar sakta tha.

Exercise 4.2 (L4)

Ek WRAP burst of 4 beats, 4-byte transfers, 0x108 se start hota hai. Ek 4-beat×4-byte burst ke liye wrap boundary $4 \times 4 = 16$ bytes hai, 0x100 se aligned. Order mein drive hone wale chaar addresses list karo.

Recall Solution

Wrap region = 16 bytes start se neeche aligned: 0x100–0x10F. 0x108 se start karo, +4 step karo, aur region se bahar jaane pe 0x100 pe wrap karo: $0 x 108 \to 0 x 10 C \to 0 x 100 \to 0 x 104$ Beat 3 (0x10C) region ka top hai; agla +4 0x110 pe hit karta jo bahar hai, toh woh aligned base 0x100 pe wrap karta hai, phir 0x104. Yeh exactly waise hai jaise ek cache line critical-word-first fill hoti hai: CPU jis word pe ruka tha wahan se start karo, phir baaqi line grab karne ke liye wrap karo.

Level 5 — Mastery

Exercise 5.1 (L5)

Handshake rule use karke explain karo kyun AXI mandate karta hai ke ek baar VALID assert ho jaane ke baad woh transfer complete hone tak high rehna chahiye (VALID withdraw nahi kiya ja sakta). Woh deadlock/data-loss scenario construct karo jo yeh rule prevent karta hai.

Recall Solution

Transfer ke liye ek edge pe $VALID \land READY$ chahiye. Maan lo VALID wait karte waqt drop ho sakta. Broken scenario: master cycle 1 pe VALID raise karta hai (wires pe data hai). Slave busy hai, READY=0. Cycle 2 pe master, impatient hokar, VALID drop karta hai aur wires change karta hai. Cycle 2 pe slave finally READY raise karta hai — lekin ab sender keh raha hai "yahan kuch valid nahi," toh beat lost ho jaata hai, ya aur bura, slave changed wires ko latch karta hai jaise woh original beat ho (data corruption). "VALID handshake tak stick karta hai" rule guarantee karta hai ke receiver ke paas hamesha ek stable, still-offered beat hoga grab karne ke liye jis moment woh READY ho jaaye. Yeh ek fragile timing race ko ek robust rendezvous mein convert karta hai. (Note karo asymmetry: READY freely drop ho sakta hai; sirf sender ka offer persistent hona chahiye.)

Exercise 5.2 (L5)

Ek designer usi master se ek slow DRAM se read aur ek fast cache pe write overlap karna chahta hai, expect karta hai ke woh parallel chalenge. Ek colleague object karta hai: "woh serialise ho jaayenge — ek bus." Kaun sahi hai, aur precisely kaun sa architectural feature yeh settle karta hai? Phir woh ek condition batao jisme ek hi address pe read aur read ko phir bhi order mein force kiya ja sake.

Recall Solution

Designer sahi hai. Write AW + W + B use karta hai; read AR + R use karta hai. Yeh physically alag channels hain, toh ek write address, write data, read address, aur read data sab ek hi cycle pe in-flight ho sakte hain. Serialise karne ke liye koi single shared data bus nahi hai — channel separation ka poora point yehi hai. Ordering exception: do reads tabhi order mein force hote hain jab unke paas same transaction ID (ARID) ho. Same-ID = ordered completion, chahe alag addresses pe ho; different-ID = reorder karne ke liye free. Toh parallelism ID assignment se limited hota hai, read/write split se nahi.

Recall Self-test recap (right side cover karo)

Kisi bhi channel pe transfer condition ::: VALID=1 AND READY=1 rising clock edge pe AXI channels ki sankhya aur kyun 6 nahi ::: 5 — read data aur read response R pe fuse ho jaate hain 16 B via 4-beat burst vs 4 singles mein percent cycles saved ::: 37.5% 4-bit ID ke saath max outstanding ::: 16 (yani 2^4) Same-ID transactions ko ::: issue order mein complete hona chahiye 0x108 se WRAP addresses, 4 beats × 4 B ::: 0x108, 0x10C, 0x100, 0x104 VALID kyun withdraw nahi ho sakta ::: READY late aane pe lost/corrupted beats prevent karne ke liye

Aage kahan jaayein

parent topic mein channel model revisit karo.
IDs aur same-address ordering memory coherence protocols se gehri tarah connect hote hain.
Bursts aur outstanding transactions DMA controllers ke liye matter karte hain jo bade blocks move karte hain.
On-chip AXI ko off-chip PCIe architecture aur broader bus architectures and topologies se compare karo.
AXI ARM ka interconnect hai — ARM architecture overview dekho.
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