AXI - AMBA on-chip protocols: Visual walkthrough — Hardware deep dive

Everything here is on-chip: wires inside a single silicon chip connecting an ARM core, caches (coherence), and DMA engines. This is not PCIe (that goes between chips).

Step 1 — Two boxes that must agree on a moment

WHAT. Picture two boxes joined by wires. The left box is the master (it starts transfers — e.g. a CPU). The right box is the slave (it responds — e.g. a memory controller). They are driven by one shared square-wave signal, the clock ACLK. A rising edge is the instant the clock jumps from 0 to 1 — that is the only moment anything is allowed to happen.

WHY. On a chip there is no "please" and "thank you" — there are only wires holding a voltage, either high (1) or low (0). Two boxes need a way to agree "now is the moment we exchange one piece of data." Guessing is not allowed; if they disagree, data is lost or duplicated.

PICTURE. The clock ticks; the vertical dashed lines mark the rising edges. Only on those lines can a transfer land.

Step 2 — One wire is not enough (the VALID-only trap)

WHAT. Give the master one wire called VALID. Rule: master raises VALID = 1 when it has data on the bus. The slave is told "whenever you see VALID, grab the data."

WHY. This is the naive design. It works only if the slave is always ready. Ask: what happens when the slave is busy finishing a previous job?

PICTURE. The master shouts VALID, but the slave's internal buffer is full (red). The data on the wire is dropped — nobody caught it. One wire cannot express "I'm not ready to catch it."

Step 3 — The other wire alone also fails (the READY-only trap)

WHAT. Now try the opposite: give the slave one wire called READY. Rule: slave raises READY = 1 when it can accept, and the master must send the moment it sees READY.

WHY. Symmetric to Step 2 — this only works if the master always has data. Ask: what if the master hasn't computed the data yet?

PICTURE. The slave shouts READY, but the master's data register is still empty (red). The slave latches garbage — whatever stale voltage happened to be on the wire.

Step 4 — The handshake: transfer on coincidence

WHAT. Keep both wires. VALID (master says "my data is real") and READY (slave says "I can take it"). The transfer happens only when both are 1 at a rising edge:

one beat moves Transfer ⟺ master’s data is valid (VALID = 1) \land slave can accept (READY = 1) \land at a rising edge ↑ ACLK

$\land$ means AND — all three must hold, not just one.
$⟺$ means "exactly when" — the left is true precisely when the right is.
$↑ ACLK$ is the rising-edge symbol from Step 1.

WHY. Each box guards its own side. A slow slave simply holds READY = 0 until ready — the master waits, nothing is lost. A slow master holds VALID = 0 — the slave waits, no garbage. Neither can force the other. This is the whole trick.

PICTURE. VALID rises at cycle 1, READY rises at cycle 2. Only at cycle 2 do the two shaded bands overlap — that green tick is the single transferred beat.

Step 5 — Every case of the handshake (nothing left uncovered)

WHAT. There are exactly four combinations of two one-bit signals. We walk all four, cycle by cycle, so no scenario surprises you.

VALID	READY	Transfer?	What is happening
0	0	No	both not ready
1	0	No	master waits for a slow slave
0	1	No	slave waits for a slow master
1	1	Yes	coincidence — one beat moves

WHY. A protocol is only trustworthy if every input combination has defined behaviour. Three of the four rows do nothing; only the all-ones row moves data. That single-row "AND gate" is what makes AXI deadlock-free and arbiter-free.

PICTURE. Two waveforms side by side: the left one is slave-slower (VALID up first, waits), the right is master-slower (READY up first, waits). Both land their transfer exactly where the bands cross.

Recall Check the handshake

If VALID is high for 5 cycles and READY is high only on the 5th, how many beats transfer? ::: Exactly one — the transfer needs the coincidence; VALID stays high (the promise) until that one cycle where READY meets it.

Step 6 — One address, many beats: the burst

WHAT. So far one handshake = one word. But memory reads usually want a contiguous chunk (a cache line). Instead of sending an address for every word, the master sends one address plus a length N; the slave then streams N data beats, auto-incrementing the address itself.

WHY. Sending an address is pure overhead — it carries no user data. If each word needs its own address cycle, half your bus time is wasted. A burst pays the address cost once and amortises it.

PICTURE. Top: four separate transactions, four address cycles (orange) interleaved with four data cycles (blue). Bottom: one address cycle then four back-to-back data beats. Same data, fewer cycles.

Worked number. Move 16 bytes = 4 words from 0x1000, each cycle = 1 unit.

Singles: $4 \times (1_{addr} + 1_{data}) = 8$ cycles.
One 4-beat INCR burst: $1_{addr} + 4_{data} = 5$ cycles.
Saving: $\frac{8 - 5}{8} = 37.5%$ .

Step 7 — Three burst flavours (cover every address pattern)

WHAT. How does the slave increment the address? Three defined modes:

FIXED — address never changes. Every beat hits the same location.
INCR — address += transfer size each beat: 0x1000, 0x1004, 0x1008, …
WRAP — like INCR but wraps back at a boundary: a 4-beat wrap from 0x100 → 0x100, 0x104, 0x108, 0x10C, 0x100, …

WHY each exists.

FIXED: a hardware FIFO register (e.g. a UART receive buffer) lives at one address; you read it repeatedly.
INCR: linear memory arrays — the natural case.
WRAP: a cache line where the critical word (the one the CPU actually missed on) comes first, then the line wraps so the rest fills without re-sending an address.

PICTURE. Three number-line strips: FIXED (one dot, revisited), INCR (dots marching right), WRAP (dots march then loop back at the wall).

Recall Which burst for a circular DMA buffer?

WRAP ::: a circular buffer is an address range that loops — WRAP does that looping in hardware for free.

Step 8 — IDs kill head-of-line blocking (the degenerate slow-reader case)

WHAT. Give every transaction a small tag: ARID (reads), AWID (writes). Responses may return out of order, and the master matches each response to its request by ID. The rule: different IDs may reorder freely; the same ID must stay in order.

WHY. The dangerous case: the master issues a slow DRAM read, then a fast cache read. Without IDs the fast read is stuck behind the slow one — "head-of-line blocking." IDs let the fast one overtake. But two writes with the same ID (e.g. update a pointer, then the data it points to) must keep order or memory consistency breaks.

PICTURE. Three reads on a timeline: ID=3 (fast SRAM, done at cycle 10) returns first; ID=5 #1 at 100; ID=5 #2 at 110 — the second ID=5 waits for the first because they share an ID.

max outstanding = 2^{W_{ID}}

$W_{ID}$ = number of ID bits.
A 4-bit ID → $2^{4} = 16$ transactions in flight at once.

The one-picture summary

WHAT. One figure that folds all eight steps together: the five AXI channels (AW, W, B for writes; AR, R for reads), each channel gated by its own VALID/READY handshake, carrying ID-tagged bursts. The handshake is the atom, the burst is the molecule, the ID is the label that lets molecules overtake.

Recall Feynman retelling — say it to a 12-year-old

Imagine two kids passing notes. If only the sender waves the note, the catcher might miss it. If only the catcher holds out a hand, the sender might have nothing to give. So they agree: you only let go of the note when the sender waves it AND the hand is out at the same tick of a clock. That's the handshake — nobody ever drops or fakes a note.

Now instead of one note, the sender says "here come four notes in a row from this shelf" — that's a burst, and it saves shouting the shelf number four times.

Finally, they put a coloured sticker on each note. Slow notes and fast notes can come back in any order, and the catcher sorts them by sticker colour — except two notes with the same colour must stay in the order they were sent, because the second one depends on the first. That's IDs. Put together, dozens of kids can pass thousands of notes at once and never lose, fake, or scramble a single one. That is AXI.