AXI - AMBA on-chip protocols: Visual walkthrough — Hinglish deep dive

6.3.7 · D2 · Hardware › Interconnects, Buses & SoC › AXI - AMBA on-chip protocols

Yahan sab kuch on-chip hai: wires ek silicon chip ke andar jo ARM core, caches (coherence), aur DMA engines ko connect karti hain. Yeh PCIe nahi hai (woh chips ke beech jaata hai).

Step 1 — Do boxes jo ek moment par agree karein

KYA. Do boxes ko wires se joda hua imagine karo. Left box hai master (yeh transfers start karta hai — jaise CPU). Right box hai slave (yeh respond karta hai — jaise memory controller). Dono ek shared square-wave signal se chalaaye jaate hain, jo hai clock ACLK. Rising edge woh instant hai jab clock 0 se 1 pe jump karta hai — yahi ek moment hai jab kuch bhi hone ki permission hai.

KYUN. Ek chip par "please" aur "thank you" nahi hota — sirf wires hote hain jo voltage hold karti hain, ya high (1) ya low (0). Do boxes ko ek tarika chahiye yeh agree karne ka ki "abhi woh moment hai jab hum data ka ek piece exchange karein." Guessing allowed nahi; agar dono disagree karein, data lost ya duplicate ho jaata hai.

PICTURE. Clock tick karta hai; vertical dashed lines rising edges mark karti hain. Sirf unhi lines par ek transfer land ho sakta hai.

Step 2 — Ek wire kaafi nahi (VALID-only trap)

KYA. Master ko ek wire do jiska naam hai VALID. Rule: master VALID = 1 raise karta hai jab uske paas bus par data hai. Slave ko bataya jaata hai "jab bhi VALID dikhe, data pakad lo."

KYUN. Yeh naive design hai. Yeh tab hi kaam karta hai jab slave hamesha ready ho. Socho: kya hoga jab slave pehla kaam khatam karne mein busy ho?

PICTURE. Master VALID chillata hai, lekin slave ka internal buffer full hai (red). Wire par data drop ho jaata hai — kisine pakda nahi. Ek wire yeh express nahi kar sakta "main pakarne ke liye ready nahi hoon."

Step 3 — Doosra akela wire bhi fail karta hai (READY-only trap)

KYA. Ab ulta try karo: slave ko ek wire do jiska naam hai READY. Rule: slave READY = 1 raise karta hai jab woh accept kar sakta hai, aur master ko READY dekhte hi send karna hoga.

KYUN. Step 2 ka symmetric case — yeh tab hi kaam karta hai jab master ke paas hamesha data ho. Socho: agar master ne abhi tak data compute nahi kiya to?

PICTURE. Slave READY chillata hai, lekin master ka data register abhi bhi empty hai (red). Slave garbage latch karta hai — jo bhi stale voltage wire par thi.

Step 4 — Handshake: coincidence par transfer

KYA. Dono wires rakho. VALID (master kehta hai "mera data real hai") aur READY (slave kehta hai "main le sakta hoon"). Transfer tab hota hai jab dono rising edge par 1 hon:

one beat moves Transfer ⟺ master’s data is valid (VALID = 1) \land slave can accept (READY = 1) \land at a rising edge ↑ ACLK

$\land$ ka matlab hai AND — teeno hold karni chahiye, sirf ek nahi.
$⟺$ ka matlab hai "exactly jab" — left tab sach hai jab right sach ho.
$↑ ACLK$ Step 1 ka rising-edge symbol hai.

KYUN. Har box apna side guard karta hai. Ek slow slave READY = 0 hold karta hai jab tak ready na ho — master wait karta hai, kuch lost nahi hota. Ek slow master VALID = 0 hold karta hai — slave wait karta hai, koi garbage nahi. Koi bhi doosre ko force nahi kar sakta. Yahi poora trick hai.

PICTURE. VALID cycle 1 par rise karta hai, READY cycle 2 par. Sirf cycle 2 par dono shaded bands overlap karti hain — woh green tick hi single transferred beat hai.

Step 5 — Handshake ke har case (kuch bhi uncovered nahi)

KYA. Do one-bit signals ke exactly char combinations hote hain. Hum char ko cycle by cycle walk karte hain taaki koi scenario surprise na kare.

VALID	READY	Transfer?	Kya ho raha hai
0	0	Nahi	dono ready nahi
1	0	Nahi	master slow slave ka wait kar raha hai
0	1	Nahi	slave slow master ka wait kar raha hai
1	1	Haan	coincidence — ek beat move hoti hai

KYUN. Ek protocol tabhi trustworthy hai jab har input combination ka defined behaviour ho. Char mein se teen rows kuch nahi karti; sirf all-ones row data move karti hai. Yeh single-row "AND gate" hi hai jo AXI ko deadlock-free aur arbiter-free banata hai.

PICTURE. Do waveforms side by side: left wala slave-slower hai (VALID pehle upar, wait karta hai), right wala master-slower hai (READY pehle upar, wait karta hai). Dono apna transfer exactly wahin land karte hain jahan bands cross karti hain.

Recall Handshake check karo

Agar VALID 5 cycles ke liye high hai aur READY sirf 5th cycle par high hai, to kitne beats transfer hote hain? ::: Exactly ek — transfer ko coincidence chahiye; VALID high rehta hai (promise) jab tak woh ek cycle na aaye jahan READY milti hai.

Step 6 — Ek address, kai beats: burst

KYA. Abhi tak ek handshake = ek word. Lekin memory reads usually ek contiguous chunk chahte hain (ek cache line). Har word ke liye address bhejne ki jagah, master ek address aur ek length N bhejta hai; slave phir N data beats stream karta hai, address khud auto-increment karte hue.

KYUN. Address bhejana pure overhead hai — yeh koi user data carry nahi karta. Agar har word ko apna address cycle chahiye, toh aadha bus time waste ho jaata hai. Ek burst address cost ek baar pay karta hai aur use amortise karta hai.

PICTURE. Upar: char alag transactions, char address cycles (orange) aur char data cycles (blue) interleaved. Neeche: ek address cycle phir char back-to-back data beats. Same data, kam cycles.

Worked number. 0x1000 se 16 bytes = 4 words move karo, har cycle = 1 unit.

Singles: $4 \times (1_{addr} + 1_{data}) = 8$ cycles.
Ek 4-beat INCR burst: $1_{addr} + 4_{data} = 5$ cycles.
Saving: $\frac{8 - 5}{8} = 37.5%$ .

Step 7 — Teen burst flavours (har address pattern cover karo)

KYA. Slave address kaise increment karta hai? Teen defined modes hain:

FIXED — address kabhi nahi badalta. Har beat same location par hit karta hai.
INCR — address += transfer size per beat: 0x1000, 0x1004, 0x1008, …
WRAP — INCR jaisa lekin ek boundary par wrap back karta hai: 0x100 se 4-beat wrap → 0x100, 0x104, 0x108, 0x10C, 0x100, …

KYUN har ek exist karta hai.

FIXED: ek hardware FIFO register (jaise UART receive buffer) ek address par rehta hai; aap baar baar wahi read karte ho.
INCR: linear memory arrays — natural case.
WRAP: ek cache line jahan critical word (woh jo CPU ne actually miss kiya) pehle aata hai, phir line wrap karti hai taaki baaki fill ho bina address dobara bheje.

PICTURE. Teen number-line strips: FIXED (ek dot, baar baar), INCR (dots right jaate hain), WRAP (dots march karte hain phir wall par loop back).

Recall Circular DMA buffer ke liye kaunsa burst?

WRAP ::: ek circular buffer hai ek address range jo loop karta hai — WRAP woh looping hardware mein free mein karta hai.

Step 8 — IDs head-of-line blocking khatam karte hain (degenerate slow-reader case)

KYA. Har transaction ko ek chhota tag do: ARID (reads), AWID (writes). Responses out of order return ho sakti hain, aur master har response ko uske request se ID ke zariye match karta hai. Rule: alag IDs freely reorder ho sakti hain; same ID order mein rehni chahiye.

KYUN. Dangerous case: master ek slow DRAM read issue karta hai, phir ek fast cache read. IDs ke bina fast read slow ke peeche stuck hai — "head-of-line blocking." IDs fast wale ko overtake karne deti hain. Lekin do writes same ID ke saath (jaise ek pointer update, phir woh data jiske taraf woh point karta hai) zaroor order rakhen warna memory consistency toot jaati hai.

PICTURE. Teen reads ek timeline par: ID=3 (fast SRAM, cycle 10 par done) pehle return karta hai; ID=5 #1 cycle 100 par; ID=5 #2 cycle 110 par — doosra ID=5 wait karta hai pehle ke liye kyunki woh ID share karte hain.

max outstanding = 2^{W_{ID}}

$W_{ID}$ = ID bits ki sankhya.
4-bit ID → $2^{4} = 16$ transactions ek saath in flight.

Ek-picture summary

KYA. Ek figure jo aathon steps ko fold karke dikhata hai: paanch AXI channels (AW, W, B writes ke liye; AR, R reads ke liye), har channel apne VALID/READY handshake se gated, ID-tagged bursts carry karte hue. Handshake atom hai, burst molecule hai, ID woh label hai jo molecules ko overtake karne deta hai.

Recall Feynman retelling — ek 12-saal ke bacche ko batao

Socho do bacche notes pass kar rahe hain. Agar sirf sender note hila ta hai, to catcher miss kar sakta hai. Agar sirf catcher haath badhata hai, to sender ke paas dene ko kuch nahi hoga. To dono agree karte hain: note tab hi chhodna jab sender hilaaye AND haath ek clock tick par baahaar ho. Yahi handshake hai — koi bhi note kabhi drop ya fake nahi hota.

Ab ek note ki jagah, sender kehta hai "yahan se chaar notes ek saath aane wale hain is shelf se" — yahi burst hai, aur yeh shelf ka number chaar baar chillane se bachata hai.

Aakhir mein, woh har note par ek coloured sticker lagaate hain. Slow notes aur fast notes kisi bhi order mein wapas aa sakte hain, aur catcher unhe sticker colour se sort karta hai — siwa is baat ke ki ek hi colour ke do notes woh order maintain karein jisme bheje gaye the, kyunki doosra pehle pe depend karta hai. Yahi IDs hain. Milaakar, dozens of bacche hazaron notes ek saath pass kar sakte hain aur ek bhi note lose, fake, ya scramble nahi hoga. Yahi AXI hai.