AXI - AMBA on-chip protocols: Foundations — Hardware deep dive

Before you can read the parent note, you must be able to look at any symbol on the page and say "I know exactly what that wire, letter, or arrow means and why it is there." This page builds every one of them from nothing. Read it top to bottom — each idea is a brick under the next.

This is the ground floor for AXI/AMBA. If you want the same material in Hinglish, see the Hinglish note.

1. The two roles: master and slave

Picture two people at a shop counter. The customer (master) says "give me item 5" or "put this on shelf 5". The shopkeeper (slave) fetches or stores it. The customer never sits behind the counter; the shopkeeper never wanders the aisles asking for things. In a chip, a CPU is usually a master, and a DRAM controller is usually a slave.

Why the topic needs this: every AXI signal has a direction — it flows from master to slave, or the reverse. You cannot read a timing diagram without knowing which side owns which wire.

Figure 1 — master starts, slave answers. The burnt-orange box on the left is the MASTER (a CPU); the teal box on the right is the SLAVE (a DRAM). The orange arrow (top) is the request travelling master→slave; the teal arrow (bottom) is the answer travelling slave→master. Notice the arrows never cross roles: the master's arrow only ever leaves the master. That directionality is the thing to burn in.

Alt-text: two labelled boxes, master (orange) and slave (teal), with a request arrow going right and an answer arrow going left.

2. A "wire" and a "signal"

Think of a signal as a light switch you can flip millions of times a second. When we write VALID = 1 we literally mean "that wire is currently at high voltage." A bundle of 32 such wires side-by-side carries a 32-bit number — that is how an address or a chunk of data travels.

Why the topic needs this: AXI is described entirely as named signals turning 1 and 0. AWVALID, WDATA, BRESP — these are all just labelled wires.

3. The clock and "rising edge"

Figure 2 — the clock and its rising edges. The teal square wave is ACLK swinging between 0 and 1. Each orange up-arrow marks a rising edge — the exact 0→1 jump. Read the caption on the arrows literally: those instants are the only moments a transfer is ever allowed to be recorded. Between two arrows, nothing "counts," no matter what the other wires do.

Alt-text: a teal square-wave clock with orange arrows pointing at each 0-to-1 transition, captioned "rising edge = photograph moment".

Why the topic needs this: the handshake rule in the parent note says a transfer happens "on the rising edge of ACLK." Without the edge concept, that sentence is meaningless.

4. VALID and READY — the handshake pair

Picture passing a plate between two hands. VALID is one hand saying "here's the plate." READY is the other hand saying "my hand is open." Only when both are true does the plate actually change hands. If one hand is closed, the plate hangs in the air, waiting — nobody drops it, nobody grabs early.

Figure 3 — the handshake, drawn. Three stacked waveforms share one time axis. Teal (bottom) is ACLK. Orange (middle) is VALID, which the sender raises early and holds high. Plum (top) is READY, which the receiver raises later. The dotted vertical line marks the first rising edge where both orange and plum are high — that is the labelled "TRANSFER here" instant. Before it, one wire is always low, so nothing moves. This picture is the AND-on-the-edge rule.

Alt-text: three waveforms — clock, VALID, READY — with a dotted line marking the single cycle where VALID and READY are both high, labelled as the transfer point.

Why the topic needs this: this single AND-on-the-edge rule governs all five channels. Learn it once, reuse it five times.

5. A "channel" — and who drives VALID/READY on each

There are five channels in AXI. Give them names now so the parent note's AW/W/B/AR/R letters aren't scary:

Picture five separate conveyor belts between master and slave. Because they are separate, an address can ride belt AW while data still rides belt W for a different request. That is the whole reason AXI is fast — the belts don't block each other.

Intuition Which side is the

sender on each channel? Recall from §4: the sender drives VALID, the receiver drives READY. So the only question per channel is "who is talking?" On the three request channels the master talks; on the two answer channels the slave talks:

Channel	Direction of the payload	Who drives VALID	Who drives READY
AW (write address)	master → slave	master (`AWVALID`)	slave (`AWREADY`)
W (write data)	master → slave	master (`WVALID`)	slave (`WREADY`)
B (write response)	slave → master	slave (`BVALID`)	master (`BREADY`)
AR (read address)	master → slave	master (`ARVALID`)	slave (`ARREADY`)
R (read data)	slave → master	slave (`RVALID`)	master (`RREADY`)

Notice the flip on B and R: because the slave is now the sender, the slave drives VALID and the master drives READY. This is the single most confusing point in AXI — the master, which drove VALID on every other channel, now drives READY and waits.

Why the topic needs this: "channel independence" is the parent's headline feature, and the parent's B/R response waveforms are unreadable unless you know that on those two channels the roles are mirrored.

6. Address, data, and "beat"

The 0x prefix just means "the number after me is written in hexadecimal (base-16)." So 0x1000 is a location label, not decimal one-thousand. Base-16 is used because chip addresses group neatly into 4-bit chunks.

Figure 4 — the AW channel, wire by wire. The orange box on the left is the master; the teal box on the right is the slave. Between them sit the AW-channel wires as labelled lanes: AWADDR (the address number), the burst-describing notes AWLEN/AWSIZE/AWBURST (defined in §7–§8), the tag AWID (§10), and at the bottom the handshake pair AWVALID (master-driven, orange) and AWREADY (slave-driven, teal). This is what "an address command" physically is: a postcard of parallel wires, guarded by one VALID/READY pair.

Alt-text: master and slave boxes with labelled AW-channel lanes between them — AWADDR, AWLEN, AWSIZE, AWBURST, AWID, and the AWVALID/AWREADY handshake pair colour-coded by who drives each.

Why the topic needs this: a "burst" is defined as many beats from one address. You must know a beat is one hand-off — and that the address itself lives on AWADDR/ARADDR — before "4-beat burst" means anything.

7. The AW-channel control signals: LEN, SIZE, BURST

Before we can talk about bursts properly, we need the three little numbers that describe a burst. They ride on the address channel alongside AWADDR itself (on the write side they are AWLEN, AWSIZE, AWBURST; the read side has identical ARLEN, ARSIZE, ARBURST).

Picture the address command as a little postcard. The postcard carries the starting address (AWADDR) plus these three notes: "send 4 of them" (LEN), "each is 4 bytes wide" (SIZE), and "step the address up each time" (BURST). The slave reads the postcard once and generates every following address itself.

Why the topic needs this: the parent note says "Send address 0x1000, length=4" — that length is AWLEN, and the "transfer size" that INCR adds each beat is set by AWSIZE. Without these three, a burst is just a word.

8. Burst and its three flavours (and the forbidden fourth)

Why bother? Sending the address costs time. If you send it once and get 4 beats, you paid the address cost once instead of four times.

AWBURST is 2 bits wide, so it can hold four values, but only three are legal:

`AWBURST`	Type	What the address does	Picture / use
0 (`00`)	FIXED	never changes	same mailbox (a FIFO buffer register)
1 (`01`)	INCR	goes up by one chunk (`2^AWSIZE` bytes) each beat	reading a normal memory array
2 (`10`)	WRAP	goes up, then jumps back at a boundary	filling a cache line / ring buffer
3 (`11`)	reserved	—	illegal — must never be used

The three legal flavours differ only in how the slave computes the next address:

Common mistake Two boundary rules the spec enforces (do not skip these)

INCR must not cross a 4 KB boundary. A single INCR burst is forbidden from stepping past any address that is a multiple of 0x1000 (4096 bytes). Why? Because 4 KB is the smallest memory-page / slave-decode granule, and a burst that spilled into the next slave would be undecodable. If your data straddles a 4 KB line, you must split it into two bursts. WRAP is strictly aligned and power-of-two length. A WRAP burst's length (in beats) must be 2, 4, 8, or 16, and the start address must be aligned to the beat size (AWSIZE). The wrap boundary is then (number of beats) × (bytes per beat), and the address rolls over exactly at that boundary — never anywhere else. This is what lets a cache fetch the critical word first and still land every word in the right slot.

Why the topic needs this: the parent's WRAP example ("4-beat wrap at 0x100") only makes sense once alignment and the wrap boundary formula are on the table; and real hardware will reject a 4 KB-crossing INCR or a reserved burst code.

9. WSTRB, WLAST, RLAST — marking which bytes and which beat

Picture the data bus as a row of 4 mailboxes (for a 32-bit bus). WSTRB is a row of 4 little flags above them. Only the mailboxes whose flag is raised get their letter delivered; the others are skipped. This is how AXI writes a single byte in the middle of a 4-byte word without disturbing its neighbours.

Why WLAST/RLAST exist even though AWLEN already gives the count: the count travels on the address channel, but the beats travel on the data channel — a separate belt (§5). The LAST flag lets the data-side hardware close out the burst without cross-referencing the address command, and it's a cheap safety check that master and slave agree on where the burst ends.

Recall Which flag, which channel, who drives it?

On a write burst, who raises WLAST and when? ::: The master, on the final W-channel data beat (WLAST = 1); 0 on all earlier beats. On a read burst, who raises RLAST? ::: The slave, on the final R-channel beat — because the slave is the sender on the R channel.

Why the topic needs this: a byte-write to a peripheral register needs WSTRB; and any burst longer than one beat is unreadable without knowing that WLAST/RLAST mark the end.

10. The transaction ID

Picture a coat-check: you hand over a coat, get ticket #5. Later you show #5 and get your coat back — even if the person behind you (ticket #3) got their coat first because it was closer. The tickets let coats come back in any order without confusion.

Why the topic needs this: "out-of-order completion" and "head-of-line blocking" are meaningless without the coat-check picture.

11. The response fields BRESP and RRESP: OKAY, EXOKAY, SLVERR, DECERR

Two bits give exactly four codes, and (unlike AWBURST) all four are defined — none reserved:

Plain pictures for each:

OKAY = the shopkeeper hands you your item, green sticker.
SLVERR = the shop exists, but something went wrong inside (e.g. you wrote to a read-only register). Red sticker, shop was real.
DECERR = you gave an address that maps to no shop at all; the interconnect's address decoder can't find anyone, so it answers on the slave's behalf. Red sticker, shop never existed.
EXOKAY = special reward for exclusive access (the hardware building block for locks): the master did a paired "read-exclusive then write-exclusive," and EXOKAY means "nobody else touched this location in between — your lock held." A plain OKAY on an exclusive write means "someone did touch it — your lock failed, try again."

For a multi-beat read burst, each beat carries its own RRESP, but a write burst gets one BRESP for the whole burst (that's why B stands for buffered response — the slave collects all beats, then answers once).

Recall Which code, which situation?

You write to 0xDEAD0000 where no peripheral is mapped. Which BRESP? ::: DECERR — the decoder found no slave. Your exclusive write returns OKAY on BRESP instead of EXOKAY. What happened? ::: Another master modified the location between your exclusive read and write; the atomic operation failed.

Why the topic needs this: the parent says "success/fail comes with data" and stresses that writes need an acknowledgement — but "fail" has three distinct kinds, it lives in the named fields BRESP/RRESP, and EXOKAY is the whole reason AXI can build spinlocks. A reader who thinks RESP is one bit will misread every response waveform.

Prerequisite map

Read it bottom-up: wires feed clocking and handshakes, handshakes build channels, channels carry the address (AWADDR), the burst-describing signals, byte strobes and last-beat flags, and bursts plus out-of-order completion plus response codes — all of that is AXI.

Bus architectures & topologies — why a single shared bus fails and channels win.
Memory coherence protocols — why same-ID ordering and exclusive access (EXOKAY) matter for consistency.
DMA controllers — a classic AXI master that isn't a CPU.
ARM architecture overview — AMBA is ARM's family.
PCIe architecture — an off-chip cousin with the same "packet + ordering" ideas.

Equipment checklist

Cover the right side and answer aloud. If any stumps you, re-read that section.

What boundary

What does a master do versus a slave?

Master starts a request (asks for/gives data); slave answers (holds the memory/register).

What is a "rising edge" and why do AXI events only happen there?

The instant the clock goes 0→1; it's the agreed moment when wire values are stable and both sides read the same thing.

Who drives VALID, who drives READY?

Sender drives VALID ("my data is real"); receiver drives READY ("I have room").

What does the symbol

⟺

mean?

"If and only if" / "exactly when" — a two-way promise: each side guarantees the other.

State the exact condition for a transfer.

VALID=1 AND READY=1 at a rising ACLK edge.

Once VALID goes high, may the sender drop it before the transfer?

No — dropping it early could cause a deadlock; it must stay high until READY meets it.

What is a channel?

A bundle of signals carrying one kind of thing, guarded by its own private VALID/READY pair.

On the B and R channels, who drives VALID?

The slave (it is the sender), so the master drives READY — the mirror of the request channels.

Name the five channels and what each carries.

AW=write address, W=write data, B=write response, AR=read address, R=read data+response.

What signal carries the actual write/read address?

AWADDR on the AW channel; ARADDR on the AR channel.

What is a "beat"?

One VALID+READY data transfer on a rising edge — one chunk handed over.

What do AWLEN, AWSIZE, AWBURST each encode?

AWLEN = beats minus one; AWSIZE = bytes per beat as a power of two; AWBURST = 0 FIXED / 1 INCR / 2 WRAP.

What is AWBURST = 3?

A reserved, illegal encoding — never used.

Why does a burst save time?

One address command serves N beats, so address cost is amortized: cost/beat = T_addr/N + T_data.