AXI - AMBA on-chip protocols: Foundations — Hinglish deep dive

6.3.7 · D1 · Hardware › Interconnects, Buses & SoC › AXI - AMBA on-chip protocols

Parent note padhne se pehle, tumhein koi bhi symbol dekh ke yeh bol paana chahiye: "mujhe bilkul pata hai yeh wire, letter, ya arrow kya matlab rakhta hai aur kyun hai." Yeh page har ek cheez ko scratch se build karta hai. Upar se neeche padho — har idea agले ke liye ek brick hai.

Yeh AXI/AMBA ka ground floor hai. Agar tum same material Hinglish mein chahte ho, toh the Hinglish note dekho.

1. Do roles: master aur slave

Do logon ko ek shop counter par imagine karo. Customer (master) kehta hai "item 5 do" ya "item 5 shelf par rakh do." Shopkeeper (slave) use fetch ya store karta hai. Customer kabhi counter ke peeche nahi baithta; shopkeeper kabhi aisles mein nahi ghoomta cheezein maangne ke liye. Ek chip mein, CPU usually ek master hota hai, aur DRAM controller usually ek slave hota hai.

Yeh topic kyun zaroori hai: har AXI signal ki ek direction hoti hai — woh master se slave ki taraf flow karta hai, ya ulti direction mein. Bina yeh jaane ki kaun si side kaun sa wire own karti hai, tum timing diagram nahi padh sakte.

Figure 1 — master shuru karta hai, slave jawaab deta hai. Left side ka burnt-orange box MASTER hai (ek CPU); right side ka teal box SLAVE hai (ek DRAM). Orange arrow (upar) request hai jo master→slave ki taraf ja raha hai; teal arrow (neeche) jawaab hai jo slave→master ki taraf ja raha hai. Notice karo arrows kabhi roles cross nahi karte: master ka arrow sirf master se hi nikalta hai. Yahi directionality hai jo yaad rakhni chahiye.

Alt-text: do labelled boxes, master (orange) aur slave (teal), ek request arrow right ki taraf aur ek answer arrow left ki taraf.

2. Ek "wire" aur ek "signal"

Signal ko ek light switch ki tarah socho jo tum ek second mein laakhon baar flip kar sakte ho. Jab hum VALID = 1 likhte hain toh literally matlab hai "woh wire abhi high voltage par hai." 32 aisi wires ka ek bundle side-by-side ek 32-bit number carry karta hai — isi tarah ek address ya ek chunk of data travel karta hai.

Yeh topic kyun zaroori hai: AXI poori tarah named signals ke 1 aur 0 hone ke terms mein describe ki jaati hai. AWVALID, WDATA, BRESP — yeh sab sirf labelled wires hain.

3. Clock aur "rising edge"

Figure 2 — clock aur uske rising edges. Teal square wave ACLK hai jo 0 aur 1 ke beech swing karta hai. Har orange up-arrow ek rising edge mark karta hai — woh exact 0→1 jump. Arrows par caption literally padho: woh instants hi sirf woh moments hain jab ek transfer record hone ki kabhi permission hai. Do arrows ke beech, kuch bhi "count" nahi hota, chahe baaki wires kuch bhi karein.

Alt-text: ek teal square-wave clock jisme orange arrows har 0-to-1 transition par point kar rahe hain, caption hai "rising edge = photograph moment".

Yeh topic kyun zaroori hai: parent note mein handshake rule kehta hai transfer "on the rising edge of ACLK" hota hai. Edge concept ke bina, woh sentence meaningless hai.

4. VALID aur READY — handshake pair

Do haathon ke beech ek plate pass karne ki tasveer socho. VALID ek haath ka "yeh lo plate" kehna hai. READY doosre haath ka "mera haath khula hai" kehna hai. Sirf jab dono true hoon tabhi plate actually haath badalta hai. Agar ek haath band hai, plate hawaon mein hang karta hai, wait karta hai — koi drop nahi karta, koi jaldi grab nahi karta.

Figure 3 — handshake, draw kiya hua. Teen stacked waveforms ek time axis share karte hain. Teal (neeche) ACLK hai. Orange (beech mein) VALID hai, jo sender early raise karta hai aur high rakhta hai. Plum (upar) READY hai, jo receiver baad mein raise karta hai. Dotted vertical line pehla rising edge mark karta hai jahan dono orange aur plum high hain — wahi labelled "TRANSFER here" instant hai. Pehle, ek wire hamesha low hoti hai, toh kuch move nahi hota. Yeh picture hi AND-on-the-edge rule hai.

Alt-text: teen waveforms — clock, VALID, READY — ek dotted line ke saath jo woh single cycle mark karta hai jahan VALID aur READY dono high hain, transfer point ki tarah label kiya gaya hai.

Yeh topic kyun zaroori hai: yeh single AND-on-the-edge rule saare paanch channels govern karta hai. Ek baar seekho, paanch baar reuse karo.

5. Ek "channel" — aur kaun VALID/READY drive karta hai har channel par

AXI mein paanch channels hain. Inhe abhi naam do taaki parent note ke AW/W/B/AR/R letters scary na lagein:

Master aur slave ke beech paanch alag conveyor belts socho. Kyunki yeh alag hain, ek address belt AW par ride kar sakta hai jabki data abhi bhi belt W par ride kar raha hai kisi doosri request ke liye. Yahi poora reason hai AXI fast hai — belts ek doosre ko block nahi karte.

Intuition Har channel par

sender kaun hai? §4 se yaad karo: sender VALID drive karta hai, receiver READY drive karta hai. Toh har channel par bas ek hi sawaal hai: "kaun baat kar raha hai?" Teen request channels par master baat karta hai; do answer channels par slave baat karta hai:

Channel	Payload ki direction	Kaun VALID drive karta hai	Kaun READY drive karta hai
AW (write address)	master → slave	master (`AWVALID`)	slave (`AWREADY`)
W (write data)	master → slave	master (`WVALID`)	slave (`WREADY`)
B (write response)	slave → master	slave (`BVALID`)	master (`BREADY`)
AR (read address)	master → slave	master (`ARVALID`)	slave (`ARREADY`)
R (read data)	slave → master	slave (`RVALID`)	master (`RREADY`)

B aur R par flip notice karo: kyunki slave ab sender hai, slave VALID drive karta hai aur master READY drive karta hai. Yeh AXI mein sabse confusing point hai — master, jo har doosre channel par VALID drive karta tha, ab READY drive karta hai aur wait karta hai.

Yeh topic kyun zaroori hai: "channel independence" parent ka headline feature hai, aur parent ke B/R response waveforms unreadable hain jab tak tum yeh nahi jaante ki un do channels par roles mirror hote hain.

6. Address, data, aur "beat"

0x prefix ka matlab sirf hai "mere baad wala number hexadecimal (base-16) mein likha gaya hai." Toh 0x1000 ek location label hai, decimal one-thousand nahi. Base-16 use hoti hai kyunki chip addresses 4-bit chunks mein neat group ho jaate hain.

Figure 4 — AW channel, wire by wire. Left side ka orange box master hai; right side ka teal box slave hai. Unke beech AW-channel wires labelled lanes ki tarah hain: AWADDR (address number), burst-describing notes AWLEN/AWSIZE/AWBURST (§7–§8 mein define), tag AWID (§10), aur neeche handshake pair AWVALID (master-driven, orange) aur AWREADY (slave-driven, teal). Yahi hai "ek address command" physically: parallel wires ka ek postcard, ek VALID/READY pair se guard kiya hua.

Alt-text: master aur slave boxes ke beech labelled AW-channel lanes — AWADDR, AWLEN, AWSIZE, AWBURST, AWID, aur AWVALID/AWREADY handshake pair colour-coded is hisab se ki kaun har ek drive karta hai.

Yeh topic kyun zaroori hai: ek "burst" define hota hai ek address se kai beats ki tarah. Tumhein pehle pata hona chahiye ki ek beat ek hand-off hai — aur address khud AWADDR/ARADDR par rehta hai — tabhi "4-beat burst" kuch matlab rakhta hai.

7. AW-channel control signals: LEN, SIZE, BURST

Bursts ke baare mein properly baat karne se pehle, humein woh teen chhote numbers chahiye jo ek burst describe karte hain. Yeh address channel par AWADDR ke saath ride karte hain (write side par yeh AWLEN, AWSIZE, AWBURST hain; read side ke paas identical ARLEN, ARSIZE, ARBURST hain).

Address command ko ek chhote postcard ki tarah socho. Postcard starting address carry karta hai (AWADDR) plus yeh teen notes: "4 bhejo" (LEN), "har ek 4 bytes wide hai" (SIZE), aur "har baar address upar step karo" (BURST). Slave postcard ek baar padhta hai aur baaki saare addresses khud generate karta hai.

Yeh topic kyun zaroori hai: parent note kehta hai "Send address 0x1000, length=4" — woh length AWLEN hai, aur "transfer size" jo INCR har beat add karta hai woh AWSIZE se set hoti hai. In teen ke bina, burst sirf ek word hai.

8. Burst aur uske teen flavours (aur woh forbidden fourth)

Kyun bothered hona? Address bhejna time leta hai. Agar tum ise ek baar bhejo aur 4 beats milo, toh tumne address cost ek baar pay ki instead of chaar baar.

AWBURST 2 bits wide hai, toh woh chaar values hold kar sakta hai, lekin sirf teen legal hain:

`AWBURST`	Type	Address kya karta hai	Picture / use
0 (`00`)	FIXED	kabhi nahi badalta	same mailbox (ek FIFO buffer register)
1 (`01`)	INCR	har beat mein ek chunk upar jaata hai (`2^AWSIZE` bytes)	normal memory array padhna
2 (`10`)	WRAP	upar jaata hai, phir ek boundary par wapas jump karta hai	cache line fill karna / ring buffer
3 (`11`)	reserved	—	illegal — kabhi use mat karo

Teen legal flavours sirf is mein differ karte hain ki slave agla address kaise compute karta hai:

Common mistake Do boundary rules jo spec enforce karta hai (inhe skip mat karo)

INCR ko 4 KB boundary cross nahi karni chahiye. Ek single INCR burst ko kisi bhi aise address ke paas jaane se forbid kiya gaya hai jo 0x1000 (4096 bytes) ka multiple ho. Kyun? Kyunki 4 KB sabse chhota memory-page / slave-decode granule hai, aur ek burst jo agले slave mein spill ho woh undecodable hogi. Agar tumhara data ek 4 KB line cross karta hai, toh tumhe use do bursts mein split karna hoga. WRAP strictly aligned aur power-of-two length hota hai. WRAP burst ki length (beats mein) 2, 4, 8, ya 16 honi chahiye, aur starting address ko beat size (AWSIZE) ke saath aligned hona chahiye. Wrap boundary phir (number of beats) × (bytes per beat) hoti hai, aur address exactly us boundary par roll over karta hai — kabhi aur kahin nahi. Yahi ek cache ko critical word first fetch karne deta hai aur phir bhi har word sahi slot mein land hota hai.

Yeh topic kyun zaroori hai: parent ka WRAP example ("4-beat wrap at 0x100") sirf tabhi samajh aata hai jab alignment aur wrap boundary formula table par hon; aur real hardware will reject karega ek 4 KB-crossing INCR ya ek reserved burst code.

9. WSTRB, WLAST, RLAST — kaun se bytes aur kaun sa beat mark karna

Data bus ko 4 mailboxes ki ek row ki tarah socho (32-bit bus ke liye). WSTRB unke upar 4 chhote flags ki row hai. Sirf jinke flag raise hain unhi mailboxes mein letter deliver hota hai; baaki skip ho jaate hain. Isi tarah AXI ek 4-byte word ke beech mein ek single byte likhta hai apne neighbors ko disturb kiye bina.

WLAST/RLAST kyun exist karte hain jabki AWLEN pehle se count deta hai: count address channel par travel karta hai, lekin beats data channel par travel karte hain — alag belt (§5). LAST flag data-side hardware ko burst close karne deta hai bina address command cross-reference kiye, aur yeh ek sasta safety check hai ki master aur slave agree karte hain burst kahan khatam hota hai.

Recall Kaun sa flag, kaun sa channel, kaun drive karta hai?

Ek write burst par, WLAST kaun raise karta hai aur kab? ::: Master, final W-channel data beat par (WLAST = 1); saare pehle beats par 0. Ek read burst par, RLAST kaun raise karta hai? ::: Slave, final R-channel beat par — kyunki slave R channel par sender hai.

Yeh topic kyun zaroori hai: ek peripheral register par byte-write ko WSTRB chahiye; aur ek beat se zyada lambi koi bhi burst unreadable hai bina yeh jaane ki WLAST/RLAST end mark karte hain.

10. Transaction ID

Coat-check socho: tum coat hand over karte ho, ticket #5 milta hai. Baad mein tum #5 dikhate ho aur apna coat wapas milta hai — chahe tumhare peeche wala (ticket #3) pehle apna coat le gaya kyunki woh closer tha. Tickets coats ko kisi bhi order mein wapas aane dete hain bina confusion ke.

Yeh topic kyun zaroori hai: "out-of-order completion" aur "head-of-line blocking" coat-check picture ke bina meaningless hain.

11. Response fields BRESP aur RRESP: OKAY, EXOKAY, SLVERR, DECERR

Do bits exactly chaar codes deti hain, aur (AWBURST ke unlike) saare chaar defined hain — koi reserved nahi:

Har ek ke liye plain pictures:

OKAY = shopkeeper tumhara item de deta hai, green sticker.
SLVERR = shop exist karta hai, lekin andar kuch galat ho gaya (e.g. tumne ek read-only register mein likha). Red sticker, shop real tha.
DECERR = tumne ek aisa address diya jo kisi bhi shop map nahi hota; interconnect ka address decoder kisi ko nahi dhundh sakta, toh woh slave ki taraf se jawaab deta hai. Red sticker, shop kabhi tha hi nahi.
EXOKAY = exclusive access ke liye special reward (locks ke liye hardware building block): master ne paired "read-exclusive phir write-exclusive" kiya, aur EXOKAY matlab hai "beech mein kisi aur ne yeh location touch nahi kiya — tumhara lock held." Ek exclusive write par plain OKAY matlab hai "kisi ne touch kiya — tumhara lock fail ho gaya, dobara koshish karo."

Ek multi-beat read burst ke liye, har beat apna RRESP carry karta hai, lekin ek write burst ko poore burst ke liye ek BRESP milta hai (isliye B buffered response ke liye stand karta hai — slave saare beats collect karta hai, phir ek baar jawaab deta hai).

Recall Kaun sa code, kaun si situation?

Tum 0xDEAD0000 par write karte ho jahan koi peripheral mapped nahi hai. Kaun sa BRESP? ::: DECERR — decoder ko koi slave nahi mila. Tumhara exclusive write BRESP par EXOKAY ki jagah OKAY return karta hai. Kya hua? ::: Ek doosre master ne tumhare exclusive read aur write ke beech location modify kar diya; atomic operation fail ho gaya.

Yeh topic kyun zaroori hai: parent kehta hai "success/fail data ke saath aata hai" aur stress karta hai ki writes ko acknowledgement chahiye — lekin "fail" ke teen distinct kinds hain, yeh named fields BRESP/RRESP mein rehta hai, aur EXOKAY poori wajah hai ki AXI spinlocks build kar sakta hai. Jo reader sochta hai RESP ek bit hai woh har response waveform galat padh lega.

Prerequisite map

Ise neeche se upar padho: wires clocking aur handshakes ko feed karte hain, handshakes channels build karte hain, channels address carry karte hain (AWADDR), burst-describing signals, byte strobes aur last-beat flags, aur bursts plus out-of-order completion plus response codes — yeh sab AXI hai.

Bus architectures & topologies — kyun ek single shared bus fail hoti hai aur channels jeet jaate hain.
Memory coherence protocols — kyun same-ID ordering aur exclusive access (EXOKAY) consistency ke liye matter karte hain.
DMA controllers — ek classic AXI master jo CPU nahi hai.
ARM architecture overview — AMBA ARM ki family hai.
PCIe architecture — ek off-chip cousin jisme same "packet + ordering" ideas hain.

Equipment checklist

Right side cover karo aur zyaan se jawaab do. Agar koi stumps kare, woh section dobara padho.

Kaun si boundary---

Master kya karta hai slave ke mukable mein?

Master ek request shuru karta hai (data maangta hai / deta hai); slave jawaab deta hai (memory/register hold karta hai).

"Rising edge" kya hai aur AXI events sirf wahan kyun hote hain?

Woh instant jab clock 0→1 hoti hai; yeh woh agreed moment hai jab wire values stable hoti hain aur dono sides ek hi cheez padhte hain.

VALID kaun drive karta hai, READY kaun?

Sender VALID drive karta hai ("mera data real hai"); receiver READY drive karta hai ("mere paas jagah hai").

Symbol

⟺

ka kya matlab hai?

"If and only if" / "exactly when" — ek do-taraf ka promise: har side doosri side guarantee karta hai.

Transfer ke liye exact condition batao.

VALID=1 AND READY=1 ek rising ACLK edge par.

Jab VALID high ho jaaye, kya sender ise transfer se pehle drop kar sakta hai?

Nahi — ise jaldi drop karna deadlock cause kar sakta hai; ise high rakhna zaroori hai jab tak READY us se na mile.

Channel kya hai?

Ek signals ka bundle jo ek tarah ki cheez carry karta hai, apne private VALID/READY pair se guard kiya hua.

B aur R channels par VALID kaun drive karta hai?

Slave (woh sender hai), toh master READY drive karta hai — request channels ka mirror.

Paanch channels ke naam batao aur har ek kya carry karta hai.

AW=write address, W=write data, B=write response, AR=read address, R=read data+response.

Actual write/read address kaun sa signal carry karta hai?

AW channel par AWADDR; AR channel par ARADDR.

"Beat" kya hai?

Ek rising edge par ek VALID+READY data transfer — ek chunk hand over kiya gaya.

AWLEN, AWSIZE, AWBURST har ek kya encode karta hai?

AWLEN = beats minus one; AWSIZE = bytes per beat power of two ki tarah; AWBURST = 0 FIXED / 1 INCR / 2 WRAP.

AWBURST = 3 kya hai?

Ek reserved, illegal encoding — kabhi use nahi hota.

Burst time kyun bachata hai?

Ek address command N beats serve karta hai, toh address cost amortized ho jaati hai: cost/beat = T_addr/N + T_data.

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