Question bank — AXI - AMBA on-chip protocols

True — channels physically alag wire bundles hain jinke apne VALID/READY pairs hain, isliye AW, W, B, AR aur R sab usi rising edge par bina kisi contention ke handshake kar sakte hain.

False — APB unpipelined aur single-transaction hai; AXI ka poora point independent address/data channels, outstanding transactions aur out-of-order completion hai. Width toh sabse chhota difference hai.

False — reads mein data hi response hai: R channel par har read data beat mein ek RRESP status field hoti hai, isliye koi chhatha channel nahi chahiye.

False — VALID tab tak high rehni chahiye jab tak transfer complete na ho jaaye (VALID aur READY dono ek rising edge par high hon). Usse pehle drop karna handshake ko deadlock kar dega aur protocol violate karega.

True — ek slave READY ko pre-assert kar sakta hai wait karte waqt; transfer simply usi cycle mein hota hai jab VALID bhi high hoti hai. Sirf VALID par "hold until transfer" rule lagta hai, READY par nahi.

False — alag IDs kisi bhi order mein complete ho sakte hain (yahi toh IDs ka point hai). Sirf same ID share karne wale transactions ka ordered hona guaranteed hai.

True — length (beat count) aur size (bytes/beat) byte count determine karte hain; INCR vs WRAP sirf kaunse addresses hit hote hain yeh change karta hai, beats ki sankhya nahi.

False — yahi toh uska purpose hai: ek FIFO/peripheral register (jaise UART RX buffer) ko drain karna jahan har read ek fixed address se naya data pop karta hai.

False — bursts address cost ko kaafi beats par amortize karte hain; ek akela single-beat transfer koi amortization nahi paata ($T_{\text{addr}}$ poora bharni padti hai). Bursts sirf tab jeette hain jab $N>1$ ho.

Error — koi bhi transfer tab tak nahi hota jab tak dono VALID aur READY usi edge par high na hon. READY 0 par atak jaaye toh kuch transfer nahi hoga; channel fast nahi, stall hai.

Error — ek $W$-bit ID $2^W$ distinct tags deta hai, isliye 3 bits $2^3=8$ outstanding allow karte hain, 3 nahi. Count ID values ki sankhya hai, bit width nahi.

Error — sequentially badhte addresses jo roll over nahi karte woh INCR burst hain. WRAP tab hota hai jab address ko ek boundary par fold back karna ho (cache-line fills ke liye), open-ended array scans ke liye nahi.

Zaruri nahi ki yeh error ho, lekin yeh claim ki yeh forbidden hai woh galat hai — AXI AW ko W se pehle force nahi karta; W data apne AW address se aage, peeche, ya saath aa sakta hai jab tak woh AWID share karein. (B response, haan, write commit hone ke baad hi aata hai.)

Error — AXI ek single shared time-slot bus nahi hai. Independent channels aur transaction IDs fast DRAM read ko slow peripheral ke peeche wait kiye bina complete hone dete hain.

Error — same ID ek possible dependency imply karta hai (jaise ek pointer write ek payload write se pehle). Same-ID transactions ko reorder karna memory consistency tod sakta hai, isliye spec isse forbid karta hai.

Kyunki address traffic data ke comparison mein chhoti hoti hai, aur decoupling master ko pipeline karne deta hai: address N+1 issue karo jabki data N abhi bhi stream ho raha ho, toh address bandwidth aur data bandwidth independently scale karte hain.

Write ki success sirf tab pata chalti hai jab slave buffered data commit kar de, jo last W beat ke baad hota hai — isliye acknowledgement ek alag, baad wala signal hona chahiye. Read ki success wapas aate R data ke andar hi hoti hai.

Agar VALID READY ke low rehte waqt drop ho sakti, toh dono sides baar baar miss kar sakti hain ya initiator ek aadha-offered transfer abandon kar sakta — yeh ek deadlock/loss hazard hai. VALID hold karna eventual coincidence aur forward progress guarantee karta hai.

IDs ke bina, responses ko issue order mein wapas aana padta, toh ek slow access (DRAM) baad wale har fast wale ko freeze kar deta. IDs har response ko uske request se independently match karne dete hain, isliye ek fast SRAM read (alag ID) ek stalled DRAM read ko overtake kar sakta hai.

Single address cost $T_{\text{addr}}$ ko $N$ beats par spread kiya jaata hai, jo per-transfer overhead $T_{\text{addr}}/N+T_{\text{data}}$ deta hai; jab $N\to \infty$ toh $T_{\text{addr}}/N$ term khatam ho jaata hai aur sirf unavoidable data time bachta hai.

VALID/READY coincidence rule ek master aur ek slave ke beech poori tarah local hai — har pair apna transfer khud negotiate karta hai, isliye flow control distributed hai aur kaafi endpoints tak scale karta hai (arbitrated shared buses se contrast ke liye 6.3.01-bus-architectures-and-topologies dekho).

Nahi — burst length kam se kam ek beat encode karta hai (AXI4 mein length field 0 ka matlab ek beat hai, zero nahi). Har valid transaction kam se kam ek data beat transfer karta hai, isliye koi "empty" transfer nahi hota.

Jo pehle issue hua woh pehle wapas aana chahiye, speed se koi fark nahi, kyunki same-ID transactions ordered hain. Agar slow wala pehle issue hua tha, toh fast wala uske peeche wait karega — yeh same-ID ordering ki keemat hai.

0x100, 0x104, 0x108, 0x10C, phir wapas 0x100 par wrap ho jaata hai continuation ke liye. Wrap boundary (beats × size) par aligned hoti hai, isliye yeh 16-byte block edge par fold karta hai aur aage nahi jaata.

Koi transfer nahi — handshake ke liye coincidence ko ek rising ACLK edge par sampled hona zaroori hai. AXI ek synchronous protocol hai; edges ke beech levels data move nahi karte.

Usse stall karna padega (naya VALID low rakhna ya wait karna) jab tak koi outstanding transaction retire na ho, kyunki sirf $2^{W_{\text{ID}}}$ tags (yahaan 16) in flight ho sakte hain; 17th ko label karne ke liye koi free ID nahi hai.

Nahi — read aur write channels by default independent hain aur ek doosre ke relative unordered hain. Dono ke beech ordering master (ya coherency logic, dekho 6.3.04-memory-coherence-protocols) ko enforce karni padegi, AXI se assume nahi kar sakte.