Worked examples — AXI - AMBA on-chip protocols

6.3.7 · D3 · Hardware › Interconnects, Buses & SoC › AXI - AMBA on-chip protocols

Yeh AXI/AMBA On-Chip Protocols ka practice arena hai. Parent note ne ideas build kiye the: paanch channels, VALID/READY handshake, bursts, aur transaction IDs. Yahan hum arithmetic karte hain — har burst type, har timing edge case, har degenerate input — taaki exam ya waveform mein koi bhi scenario surprise na kare.

Agar koi symbol neeche unfamiliar lage, toh woh parent mein define kiya gaya tha. Doubt ho toh the AXI topic note revisit karo, ya neighbouring bus architectures note dekho.

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Pehle, vocabulary (taaki yeh page akela khada rahe)

Bhale hi parent ne yeh sab banaya, lekin chaliye har symbol ko re-introduce karte hain jo hum use karte hain, taaki tumhe kabhi yeh page chhodna na pade.

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Scenario matrix

Kisi bhi example se pehle, chaliye un cases ko enumerate karte hain jo ek AXI question tumpar throw kar sakta hai. Isse socho jaise trigonometry karne se pehle har quadrant list karna — humein zero blind spots chahiye.

Real question space $3\times 2\times 2=12$ combinations hai: teen burst types (INCR/WRAP/FIXED) × do handshake-stall sides (slave-slow / master-slow) × do ID relationships (same-ID / different-ID). Hum deliberately 12 combinations mein se har ek ko cover karte hain — kuch examples ek se zyada cells carry karte hain taaki table readable rahe.

Cell	Case class	Kya tricky banata hai	Example(s) jo ise hit karte hain
A	Handshake — slave slower	VALID ko READY tak hold karna padta hai	Ex 1
B	Handshake — master slower	READY wait karta hai, koi data lost nahi	Ex 2
C	Burst INCR efficiency	address amortization $T_{addr}/N$	Ex 3
D	Burst WRAP wrap-around	address ek boundary par fold karta hai	Ex 4
E	Burst FIXED (degenerate)	address kabhi nahi hilta ($N$ beats, 1 address)	Ex 5
F	Out-of-order by ID	alag IDs reorder karte hain, same ID serialize karta hai	Ex 6
G	Zero / limiting input	1-beat "burst", $N\to \infty$ limit	Ex 7
H	Real-world word problem	mixed read+write, channel overlap	Ex 8
I	Exam twist	narrow transfer + unaligned start	Ex 9

Poora $3\times 2\times 2$ grid bharna. Upar ke naun examples distinct phenomena cover karte hain; remaining combinations wahi phenomena ek saath stack hue hain. Example 10 grid ko explicitly close karta hai ek stalled handshake jo har burst type ke andar ho raha hai, dono same-ID aur different-ID streams ke saath — woh cells jo ek single-topic example apne dum par nahi reach karta.

Burst type	slave-slow, diff-ID	slave-slow, same-ID	master-slow, diff-ID	master-slow, same-ID
INCR	Ex 3 + Ex 1 pattern	Ex 10 (a)	Ex 3 + Ex 2 pattern	Ex 10 (b)
WRAP	Ex 4 + Ex 1 pattern	Ex 10 (c)	Ex 4 + Ex 2 pattern	Ex 10 (c)
FIXED	Ex 5 + Ex 1 pattern	Ex 10 (d)	Ex 5 + Ex 2 pattern	Ex 10 (d)

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Cell A — Slave master se slower

Forecast: aage padhne se pehle transfer cycle guess karo. (Hint: handshake rule ko dono signals chahiye.)

Neeche ki figure ek timing diagram hai: time left-to-right clock cycles mein chalta hai, aur har horizontal line ek signal hai — high = logic 1, low = logic 0. Magenta VALID line pehle high jaati hai aur rehti hai; violet READY line late hai; orange dashed line wahan mark karti hai jahan dono coincide karte hain.

Figure 1 — Slave-slower handshake. VALID (magenta) cycle 0 par assert hota hai aur high hold rehta hai; READY (violet) sirf cycle 3 par rise karta hai; orange dashed line woh transfer mark karta hai jahan dono 1 hain.

1. Handshake rule likho. Transfer tab hota hai jab $\text{VALID}=1\wedge \text{READY}=1$ ek rising clock edge par. Figure mein, yeh exactly wahan hai jahan magenta aur violet lines dono high hain.
   • Yeh step kyun? Yeh wahi moment hai jab transfer define hota hai. Coincidence nahi, transfer nahi.
2. Cycle by cycle scan karo. Cycle 0–2: VALID=1 lekin READY=0 → koi transfer nahi. Cycle 3: VALID=1, READY=1 → transfer (orange dashed marker).
   • Yeh step kyun? Hum literally dono lines ko har cycle AND kar rahe hain — seedha figure se padho.
3. Hold rule apply karo. VALID cycles 0–2 ke dauran nahi gir sakta tha (magenta line flat-high rehti hai), isliye address cycle 3 par wires par hai.
   • Yeh step kyun? AXI spec VALID ko transfer complete hone se pehle drop karne se mana karta hai — yahi hai jo data loss rokta hai.

Answer: cycle 3 par transfer, kuch lost nahi.

Verify: stall cycles gino: transfer cycle $=\max (\text{VALID assert},\text{READY assert})=\max (0,3)=3$. ✓ Units clock cycles hain, consistent.

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Cell B — Master slave se slower

Forecast: kya READY ka jaldi hona slave ko undefined data accept karaata hai?

Pehle jaisa hi timing-diagram convention, lekin ab roles swap hain: violet READY pehle hai aur held hai, magenta VALID late hai. Orange dashed line phir se coincidence mark karti hai.

Figure 2 — Master-slower handshake. READY (violet) cycle 0 se high hai aur held hai; VALID (magenta) cycle 2 par rise karta hai; orange dashed line transfer mark karta hai. Kyunki VALID data gate karta hai, early READY cycle 2 tak kuch nahi grab karta.

1. Same rule, roles swap. Transfer ko dono = 1 chahiye. Figure mein, READY cycle 0 se already high hai, toh hum magenta VALID line ka wait kar rahe hain.
   • Yeh step kyun? Handshake symmetric hai — ise parwah nahi ki kaun late hai.
2. Scan karo. Cycle 0–1: READY=1, VALID=0 → koi transfer nahi (master ke paas abhi valid data nahi hai). Cycle 2: dono 1 → transfer.
   • Yeh step kyun? Kyunki VALID=0 ka matlab hai "bus par data meaningless hai," slave ko ise latch karna forbidden hai. Koi garbage nahi.
3. No loss, no garbage confirm karo. Single valid beat exactly cycle 2 par land karta hai (orange marker).

Answer: cycle 2 par transfer; koi garbage grab nahi hua.

Verify: transfer cycle $=\max (2,0)=2$. ✓ Ex 1 ke saath symmetric, as expected.

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Cell C — INCR burst efficiency

Forecast: single-beat 8 cycles cost karta hai (parent ne dikhaya). Burst cost aur % saved guess karo.

1. Single-beat cost. Har transfer = 1 address + 1 data = 2 cycles; inke chaar = $4\times 2=8$ cycles.
   • Yeh step kyun? Baseline. Har transfer $T_{addr}$ dobara pay karta hai.
2. Burst cost. Ek address (cycle 0) phir 4 data beats (cycles 1–4) = $1+4=5$ cycles.
   • Yeh step kyun? Slave internally address auto-increment karta hai: $0x1000,0x1004,0x1008,0x100C$. Sirf EK address command chahiye.
3. Saving compute karo. $\frac{8-5}{8}=0.375=37.5\%$.
   • Yeh step kyun? Eliminate kiye gaye cycles ka fraction = $T_{addr}$ ko $N$ beats par amortize karne ka payoff.

Answer: 5 cycles vs 8; 37.5% saved.

Verify: general formula ${\text{cycles}}_{\text{burst}}=T_{addr}+N{T}_{data}=1+4=5$. ✓ Step 2 se match karta hai.

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Cell D — WRAP burst wrap-around

Forecast: INCR deta 0x108, 0x10C, 0x110, 0x114. WRAP alag hai — guess karo kahan fold hota hai.

Figure 16-byte cache line ko chaar boxes ke roop mein dikhata hai; har arrow jo "beat 0…3" label hai woh us box ki taraf point karta hai jise woh beat target karta hai, aur curved navy arrow cache line ke top se wapis uske base tak fold dikhata hai.

Figure 3 — WRAP burst folding. Chaar boxes base 0x100 se shuru hone wale cache line ke 16 bytes hain. Coloured arrows beats 0–3 ko offsets 8, 12, 0, 4 par land karte dikhate hain; curved navy arrow address ko 16-byte boundary par base par wapas fold karte dikhata hai.

1. Wrap boundary dhundo. Wrap length in bytes $=N\times (\text{bytes per beat})=4\times 4=16$ bytes. Aligned region hai 0x100–0x10F.
   • Yeh step kyun? WRAP cache-line fills ke liye use hota hai: ise ek line ke andar rehna chahiye, isliye boundary burst ki byte size ke barabar hai.
2. Start se 4 se increment karte hue chalo. 0x108 → 0x10C (figure mein beats 0 aur 1).
   • Yeh step kyun? Region ke top tak pahunchne tak INCR jaisa hi increment.
3. Boundary par wrap karo. Agla hota 0x110, jo 0x10F cross karta hai. Region base par fold karo: 0x100, phir 0x104 (beats 2 aur 3, curved arrow follow karte hue).
   • Yeh step kyun? WRAP low bits wrap karta hai — critical-word-first cache fills ko pehle requested word chahiye, phir line ka baaki hissa.

Answer: 0x108, 0x10C, 0x100, 0x104.

Verify: yahan $\text{base}=\text{0x100}$ (region start) aur $\text{start}=\text{0x108}$ (burst start). Beat number $i$ ke liye (jahan $i=0,1,2,3$), address $=\text{base}+((\text{start}-\text{base})+4i)\mathrm{mod}16$. Charon beats offsets $8,12,0,4$ dete hain → 0x108,0x10C,0x100,0x104. ✓ Charon line ke andar hain.

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Cell E — FIXED burst (degenerate address)

Forecast: beat 3 kaunsa address use karta hai?

1. FIXED matlab koi increment nahi. Har beat same address 0x4000 target karta hai.
   • Yeh step kyun? Ek hardware FIFO ek register expose karta hai; har read ek new word pop karta hai lekin address kabhi nahi hilta. Increment karna wrong registers padhega.
2. Addresses: 0x4000, 0x4000, 0x4000, 0x4000.
3. Cycles: abhi bhi ek address + chaar beats = 5 cycles.
   • Yeh step kyun? Burst timing burst type se independent hai; sirf slave ka internal address math alag hota hai.

Answer: chaar identical addresses; 5 cycles.

Verify: FIXED ke liye offset formula = 0 har beat ke liye → sab 0x4000. Cycles $=1+4=5$. ✓

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Cell F — ID ke basis par Out-of-order

Forecast: kaunsa pehle return karta hai, aur second ID=5 read kab finish hoti hai?

1. Alag IDs reorder ho sakte hain. ID=3 (SRAM, 10-cycle latency) ID=5 se independent hai → uska data cycle 10 par return hota hai.
   • Yeh step kyun? AXI alag IDs wale responses ko kisi bhi order mein allow karta hai — koi head-of-line blocking nahi.
2. Pehla ID=5 cycle 100 par complete hota hai (uski stated 100-cycle DRAM latency, cycle 0 se shuru).
   • Yeh step kyun? Seedha latency, kuch block nahi karta.
3. Second ID=5 ko pehle ID=5 ka wait karna padta hai. Same ID ⇒ ordered response. Kyunki single DRAM port cycle 100 tak busy hai, second ID=5 read cycle 100 par start hoti hai aur apni khud ki 100-cycle latency leti hai, $100+100=200$ par complete hoti hai.
   • Yeh step kyun? Yahan do effects stack hote hain, aur dono same direction point karte hain: (i) same-ID responses order mein rehne chahiye, isliye yeh cycle 100 se pehle return nahi kar sakta; (ii) shared single-port DRAM pehla access cycle 100 par finish hone se pehle second access begin bhi nahi kar sakta. Second access ki khud ki 100-cycle latency add karne par cycle 200 milta hai. Yeh stated latencies se clean derivation hai — koi undefined constants nahi.

Answer: ID=3 cycle 10 par, ID=5 (#1) cycle 100 par, ID=5 (#2) cycle 200 par.

Verify: ordering predicate — ID=3 ≠ ID=5 isliye yeh pehle aa sakta hai; dono ID=5 completions $t_{\#1}<t_{\#2}$ satisfy karte hain ($100<200$), aur $t_{\#2}=t_{\#1}+100=200$. ✓

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Cell G — Zero / limiting inputs

Forecast: kya 1-beat burst kuch save karta hai?

Overhead function yaad karo jo humne vocabulary mein name kiya tha. Ab hum iska formula derive karte hain. Ek burst ek address cost $T_{addr}$ pay karta hai (sab beats mein shared) plus $T_{data}$ per beat. Total cycles $=T_{addr}+N{T}_{data}$; $N$ beats se divide karne par per transfer cost milti hai: $\text{overhead}(N)=\frac{T_{addr}+N{T}_{data}}{N}=\frac{T_{addr}}{N}+T_{data}$

Figure is function ko $N$ ke against plot karta hai: ek magenta curve 2 se 1 par violet dashed horizontal line ki taraf girta hai, dikhata hai ki $N$ badhne ke saath address cost thinner spread hoti hai.

Figure 4 — Overhead per transfer versus burst length N. Magenta curve overhead(N) = T_addr/N + T_data hai; N=1 ke liye 2 cycles se shuru hoti hai (koi saving nahi) aur N badhne ke saath violet dashed asymptote 1 cycle par fall karti hai, matlab single address cost zyada beats par amortize hoti hai.

1. $N=1$ plug karo. $\text{overhead}(1)=T_{addr}+T_{data}=1+1=2$ cycles.
   • Yeh step kyun? 1-beat burst bas ek single transaction hai — koi amortization nahi, isliye naive cost ke barabar hai. Yeh degenerate case hai jahan bursts zero benefit dete hain (curve par leftmost point).
2. Limit $N\to \infty$ lo. $\frac{T_{addr}}{N}\to 0$, isliye $\text{overhead}\to T_{data}=1$ cycle (violet dashed asymptote).
   • Yeh step kyun? Address cost ek baar pay hoti hai aur thinner aur thinner spread hoti hai. Yeh best case hai — pure data bandwidth.
3. Interpret karo. Real AXI $N$ ko 16 (INCR) ya 256 (AXI4) par cap karta hai, isliye hum limit ke kareeb pahunchte hain lekin kabhi nahi pahunchte.
   • Yeh step kyun? Mathematical limit ek ideal hai; hardware constraints ka matlab hai hum 1 cycle approach karte hain lekin kabhi touch nahi karte.

Answer: (a) 1-beat overhead $=2$ cycles; (b) $N\to \infty$ hone par, overhead $\to 1$ cycle.

Verify: $\text{overhead}(1)=\frac{1}{1}+1=2$ ✓, aur ${\lim }_{N\to \infty }\left(\frac{1}{N}+1\right)=1$ ✓. Units poore mein clock cycles hain.

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Cell H — Real-world word problem

Forecast: independent channels — guess karo kya yeh ek doosre ko block karte hain.

1. Read path. Cycle 0 par AR; DRAM ki 15-cycle latency ka matlab hai R data cycle 15 par return hota hai.
   • Yeh step kyun? Read ka write ke channel se koi lena-dena nahi — yeh sirf AR/R par run karta hai.
2. Write path — breakdown. Write teen channels sequence mein use karta hai: cycle 0 par AW (address), cycle 1 par W (data), aur cycle 2 par B (write response). Concretely: cycle 0 par address handshake complete; cycle 1 par single data beat handshake; cycle 2 par cache B assert karta hai buffered write acknowledge karne ke liye. Yeh hai address se response tak 2 cycles.
   • Yeh step kyun? Hum "2 cycles" assert nahi kar rahe — hum ek cycle per channel handshake count kar rahe hain (AW → W → B), jo exactly woh hai jaise ek fast buffered write complete hota hai.
3. Compare karo. Write 2 par done, read 15 par done. Write 13 cycles pehle finish hua, unblocked.
   • Yeh step kyun? Channel independence poori baat hai: ek fast write slow read ka hostage nahi hota (masters ke beech write ordering ke liye coherence dekho jahan IDs zaruri hain).

Answer: write cycle 2 par complete, read cycle 15 par; write ne wait nahi kiya.

Verify: write cycles $=1$ (AW) $+1$ (W→B) $=2$; $t_{\text{write}}=2<t_{\text{read}}=15$, gap $=13$. ✓

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Cell I — Exam twist: narrow transfer + unaligned start

Forecast: beat 0 mein 4 byte lanes mein se kaunse valid data carry karte hain?

1. Addresses compute karo. Transfer size = 2 bytes, isliye INCR 2 se step karta hai: 0x1002, 0x1004, 0x1006.
   • Yeh step kyun? INCR transfer size se increment karta hai, bus width se nahi. Narrow transfers chhote strides mein step karte hain.
2. Beat 0 ke liye byte lanes locate karo. Bus ke chaar lanes bytes 0x1000–0x1003 cover karte hain. Address 0x1002 bytes 2 aur 3 ke lanes occupy karta hai.
   • Yeh step kyun? 4-byte bus par, byte address mod 4 lane pick karta hai. $0x1002\mathrm{mod}4=2$ → lanes 2 aur 3.
3. Strobe likho. WSTRB = 1100 (binary): lanes 3 aur 2 active, lanes 1 aur 0 idle.
   • Yeh step kyun? WSTRB ek bit per byte lane hai jo mark karta hai kaunse lanes live data carry karte hain. Unaligned narrow writes sirf relevant lanes light up karte hain; baaki ko mask karna padta hai warna memory corrupt hoti hai.

Answer: addresses 0x1002, 0x1004, 0x1006; first-beat WSTRB = 0b1100.

Verify: step $=2$, isliye beats dete hain $0x1002,0x1004,0x1006$. Lane index $=0x1002\mathrm{mod}4=2$; 2-byte transfer lanes 2 aur 3 set karta hai → strobe bits $2^2+2^3=4+8=12=0b1100$. ✓

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Stacked grid cells fill karna — har burst type ke andar handshake stall

Forecast: ek one-cycle stall kitne cycles add karta hai, aur kya burst type ise change karta hai?

1. Baseline burst cost. Cell C se: ek clean 4-beat burst = $T_{addr}+4T_{data}=1+4=5$ cycles.
   • Yeh step kyun? Bubble add karne se pehle humein no-stall reference chahiye.
2. (a) INCR, beat 2 par ek slave stall. Stall exactly ek bubble cycle insert karta hai (READY ek cycle ke liye low), isliye total $=5+1=6$ cycles. Same-ID vs different-ID is single burst ko nahi change karta — ID sirf ise doosre bursts ke against order karta hai.
   • Yeh step kyun? Har inserted wait state ek extra cycle hai; handshake rule (transfer sirf tab jab dono high) stall cost ko exactly uski duration banata hai.
3. (b) INCR, beat 2 par master-slow stall. Symmetric: agar master ek cycle ke liye VALID drop kare, same single bubble appear hota hai → $5+1=6$ cycles. Koi bhi side stall kare farak nahi padta; cost stall ki duration hai.
   • Yeh step kyun? Handshake symmetric hai (Ex 1 vs Ex 2), isliye slave-slow aur master-slow same stall length ke liye identical timing dete hain.
4. (c) WRAP aur (d) FIXED, same stall. Burst type sirf address sequence change karta hai (Ex 4, Ex 5), kabhi timing nahi. Isliye WRAP aur FIXED bhi ek bubble ke saath $5+1=6$ cycles cost karte hain.
   • Yeh step kyun? Yeh key unification hai: timing beats aur stalls par depend karta hai; addressing burst type par depend karta hai. Yeh independent axes hain — isliye $3\times 2\times 2$ grid kuch hi rules mein collapse hota hai.

Answer: har combination = ek inserted stall ke liye 6 cycles; burst type aur stall-side timing-irrelevant hain, ID relationship sirf cross-burst ordering affect karta hai.

Verify: clean burst $=1+4=5$; ek stall 1 add karta hai → $6$ (a),(b),(c),(d) sab ke liye. ✓

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Recall drills

Recall AXI transfer actually kab hota hai?

Rising clock edge par jab VALID aur READY dono 1 hon. ::: Dono handshake signals ka coincidence.

Recall 4-beat INCR vs four singles at

$T_{addr}=T_{data}=1$ — cycles aur saving? 5 vs 8 cycles ::: 37.5% saved.

Recall

0x100 line mein 0x108 se 4-beat WRAP — chaar addresses? 0x108, 0x10C, 0x100, 0x104 ::: 16-byte boundary par fold wapas karta hai.

Recall

Same ID ke do reads — kya woh out of order complete ho sakte hain? Nahi ::: same ID in-order completion force karta hai; alag IDs reorder ho sakte hain.

Recall Kisi bhi burst type par ek one-cycle stall — kitne extra cycles?

Ek ::: burst type aur stall-side kabhi timing nahi change karte, sirf addressing/ordering.

Related: DMA controllers exactly yeh AXI bursts issue karte hain; ARM cores classic masters hain; off-chip PCIe se contrast karo jo side-band handshakes ki jagah packetize karta hai.