Worked examples — PCI Express (PCIe) architecture and generations

This page is the calculator's playground for PCI Express architecture and generations. The parent note gives you the formulas; here we drive them through every situation you could meet — the tiny x1 link, the huge x16 link, the two different encodings, the sneaky "13× vs 1.23×" trap, and a PAM-4 signal-quality problem. By the end, no exam question about PCIe throughput should surprise you.

Every number below is machine-checked. If you follow a worked example and get a different number, you found the typo, not the vault.

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The scenario matrix

Before touching a single number, let us map out every kind of question this topic can throw at you. Think of it like a chessboard: each square is a "case class", and we will make sure at least one worked example lands on every square.

Cell	What makes it different	Which example covers it
A — tiny link	$L=1$ lane (smallest, catches per-lane errors)	Example 1
B — wide link	$L=16$ lanes (aggregation)	Example 2
C — old encoding	8b/10b, efficiency $=\frac{8}{10}$	Example 1, 3
D — new encoding	128b/130b, efficiency $=\frac{128}{130}$	Example 2, 4
E — the ratio trap	"13× less waste" vs "1.23× more data"	Example 5
F — degenerate / zero	$L=0$ or "raw = usable?" edge questions	Example 6
G — full-duplex doubling	multiply by 2 for bidirectional aggregate	Example 7
H — real-world word problem	"will an SSD saturate this slot?"	Example 8
I — exam twist / PAM-4 SNR	signal-quality, $\log$, dB	Example 9

Let us pin down each knob with a picture before we compute.

What this figure shows (Figure 1 — the master pipeline). Read the diagram left to right as an assembly line that manufactures a bandwidth number. The lane-count box on the far left (lavender, and drawn as a rectangle) is your lane count $L$ — how many independent wire-pairs the link has. The arrow feeds into the raw-rate box (coral, drawn as a rounded rectangle), the raw transfer rate $R$ (in GT/s = gigatransfers per second) that each lane pushes. That feeds the efficiency box (mint, drawn as an ellipse), the encoding efficiency $E$ — always a fraction below 1, because every encoding sacrifices some bits for clock recovery and error checking. Finally the duplex box (butter, drawn as a diamond with a "?" mark because it is optional) is an optional $\times 2$: flip it on only when the question wants both directions added together. Each box is also labelled with a bold letter (L, R, E, ×2?) so you can refer to it without relying on colour. The white output box on the right (drawn with a thick double border) is the finished product — the bandwidth the exam is asking for. The italic caption under the line reminds you of the one extra move: divide by 8 if they want bytes rather than bits. Every single example below is just this same line with different numbers dropped into the four labelled boxes.

One unit fact we will lean on constantly:

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Worked examples

Example 1 — Cell A + C: the smallest possible link (x1, Gen 1)

Forecast: Guess now — will it be more or less than 312 MB/s (which is 2.5 Gb/s ÷ 8, ignoring encoding)? Because encoding throws away 20%, expect less.

Step 1 — set the knobs. $L=1$, $R=2.5$ GT/s, and since 1 transfer = 1 bit here, that is $2.5$ Gb/s of raw line rate. Why this step? We are just reading the scenario into the master formula's slots. Gen 1 is one bit per transfer, so no PAM-4 subtlety.

Step 2 — apply encoding efficiency. $E=\frac{8}{10}=0.8$. $\text{usable bits/s}=2.5\text{ Gb/s}\times 0.8=2.0\text{ Gb/s}$ Why this step? Of every 10 bits on the wire, only 8 are your data. So multiply by $0.8$.

Step 3 — convert to bytes. Divide by 8: $\frac{2.0\text{ Gb/s}}{8}=0.25\text{ GB/s}=250\text{ MB/s}$ Why this step? The question asks in MB/s (bytes), and 8 bits make a byte.

Answer: 250 MB/s.

Recall Verify: units and sanity

$2.5\text{ Gb/s}\times 0.8=2.0\text{ Gb/s}$ ✓, and $2.0/8=0.25\text{ GB/s}=250\text{ MB/s}$ ✓. This matches the parent note's Gen 1 x1 row exactly. And yes — $250<312$, as forecast, because encoding ate 20%.

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Example 2 — Cell B + D: the widest link (x16, Gen 3)

Forecast: Gen 1 x1 was 0.25 GB/s. This is 16 lanes, faster rate, better encoding. Guess a number near 15 GB/s.

Step 1 — per-lane usable bits. $8\text{ Gb/s}\times \frac{128}{130}=8\times 0.98462=7.877\text{ Gb/s per lane}$ Why this step? First find one lane's real data rate; then lanes just multiply (they are independent — no sharing).

Step 2 — aggregate 16 lanes. $16\times 7.877=126.05\text{ Gb/s}$ Why this step? Each lane is a private wire pair, so total data = one lane × lane count. No contention, so plain multiplication is valid.

Step 3 — bits to bytes. $\frac{126.05}{8}=15.76\text{ GB/s}$ Why this step? Answer requested in bytes.

Answer: ≈ 15.75 GB/s (one direction).

Recall Verify

$8\times 128/130=7.8769\dots$ Gb/s ✓; $\times 16=126.03$ Gb/s ✓; $÷8=15.754$ GB/s ✓ (rounds to the parent's Gen 3 x16 entry of 15.75 GB/s).

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Example 3 — Cell C, doubled rate (x1, Gen 2)

Forecast: Same encoding, exactly double the rate → expect exactly double Gen 1's 250, so 500 MB/s.

Step 1 — usable bits. $5.0\text{ Gb/s}\times 0.8=4.0\text{ Gb/s}$. Why this step? Same 8b/10b machine as Example 1, just faster line rate.

Step 2 — to bytes. $4.0/8=0.5\text{ GB/s}=500\text{ MB/s}$. Why this step? Byte answer requested.

Answer: 500 MB/s — exactly $2\times$ Gen 1.

Recall Verify

$5.0\times 0.8/8=0.5$ GB/s = 500 MB/s ✓, and $500=2\times 250$ ✓.

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Example 4 — Cell D, half-width middle case (x8, Gen 4)

Forecast: Gen 4 x16 is famously 31.5 GB/s (from the parent table). Half the lanes → guess ~15.75 GB/s.

Step 1 — per-lane. $16\times \frac{128}{130}=15.754$ Gb/s. Why this step? Lane rate first, always.

Step 2 — aggregate 8 lanes. $8\times 15.754=126.03$ Gb/s. Why this step? Lane count multiplies. Notice it equals Gen 3 x16 from Example 2 — twice the rate, half the lanes cancel out.

Step 3 — bytes. $126.03/8=15.75$ GB/s.

Answer: ≈ 15.75 GB/s.

Recall Verify

$16\times 128/130\times 8/8=15.754$ GB/s ✓ (rounds to 15.75). And Gen 4 x16 double this = 31.5 GB/s, matching the parent table.

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Example 5 — Cell E: the "13× vs 1.23×" ratio trap

Forecast: Two ratios are hiding. One compares wasted fractions, the other compares usable fractions. They are NOT the same and NOT interchangeable.

Step 1 — wasted fraction of each encoding. ${\text{waste}}_{8b/10b}=\frac{10-8}{10}=0.20=20\%$ ${\text{waste}}_{128b/130b}=\frac{130-128}{130}=0.01538=1.538\%$ Why this step? "Waste" is the overhead bits divided by total bits. This is what "less waste" refers to.

Step 2 — ratio of the two wastes. $\frac{20\%}{1.538\%}=13.0$ Why this step? This is the honest source of the "13×" claim — the wasted fraction shrank 13-fold.

Step 3 — but usable throughput is what you feel. Compare the efficiencies, not the wastes: $\frac{E_{128b/130b}}{E_{8b/10b}}=\frac{128/130}{8/10}=\frac{0.98462}{0.80}=1.2308$ Why this step? Since 80% was already getting through, killing the last chunk of waste only lifts you from 80% to 98.46% — a $1.23\times$ gain, not $13\times$.

Answer: $13\times$ = shrinkage of wasted bits; $1.23\times$ = growth of usable data (per lane, encoding change alone).

What this figure shows (Figure 2 — two ratios, side by side). The chart splits into two coral bars on the left and two mint bars on the right, and to stay readable without colour each waste bar is filled with a diagonal-hatch pattern while each usable bar is filled solid; every bar is also text-labelled ("waste" or "usable") right on it. The waste bars (hatched, coral) are the wasted fraction: the left one is a tall 20% (8b/10b), the right one is a stubby 1.54% (128b/130b) — and the lavender double-arrow labels the gap "13× shorter". That shrinkage is real and honest. Now move your eye to the usable bars (solid, mint), the usable-data fraction: the left is 80%, the right 98.46%, and the lavender arrow labels them "only 1.23× taller". The whole point of the picture is the contrast: the same encoding change makes the hatched waste bar collapse dramatically (13×) yet nudges the solid usable bar up only a sliver (1.23×). Your GPU feels the solid bars, not the hatched ones — so the honest per-lane data gain from the encoding change is 1.23×, never 13×.

Recall Verify

$0.20/(2/130)=13.0$ ✓; $(128/130)/(8/10)=1.2308$ ✓.

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Example 6 — Cell F: degenerate inputs (x0, and "does raw = usable?")

Before we touch this example's part (b), we must define a term the parent note used only in passing.

Forecast: (a) Zero lanes = zero data, formula must give 0. (b) No generation reaches 100% — every encoding costs something.

Step 1 — (a) plug $L=0$. $BW=0\times R\times E\times 2=0\text{ Gb/s}$ Why this step? A link with no lanes carries nothing; the formula must and does collapse to zero. This is the sanity floor — always confirm your formula gives 0 for 0 lanes.

Step 2 — (a) convert to bytes. Divide by 8: $\frac{0\text{ Gb/s}}{8}=0\text{ GB/s}$ Why this step? We still run the same final byte-conversion step every example uses, to prove it does not accidentally introduce bandwidth — zero divided by 8 is still zero, confirming the pipeline is consistent even at the degenerate input.

Step 3 — (b) check every efficiency.

• 8b/10b: $E=0.8<1$
• 128b/130b: $E=0.98462<1$
• Gen 6 FLIT: $E=\frac{242}{256}=0.9453<1$

Every one is strictly below 1. Why this step? "Efficiency = 100%" would require zero overhead bits, but clock recovery, DC balance, and error-check bits are mandatory. The closest is 128b/130b at 98.46%.

Answer: (a) 0 GB/s. (b) No — the highest efficiency is 98.46% (128b/130b); it never reaches 100%.

Recall Verify

$0\times 8\times 0.98462\times 2/8=0$ ✓; and $\max (0.8,128/130,242/256)=128/130=0.98462<1$ ✓.

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Example 7 — Cell G: the full-duplex doubling (x16, Gen 5, aggregate)

Forecast: One-direction Gen 5 x16 should be double Gen 4's 31.5 → 63 GB/s. Aggregate doubles again → 126 GB/s.

Step 1 — one-direction per lane. $32\times \frac{128}{130}=31.508$ Gb/s. Why this step? Lane rate first.

Step 2 — 16 lanes, one direction, to bytes. $\frac{16\times 31.508}{8}=63.02\text{ GB/s}$ Why this step? This is the number the parent table lists (per-direction), which rounds to 63.

Step 3 — apply the $\times 2$ for full-duplex. $63.02\times 2=126.03\text{ GB/s aggregate}$ Why this step? Because TX and RX are physically separate wire-pairs, both can run at full speed at the same time — neither steals bandwidth from the other. When a question asks for the aggregate (both directions summed), we are allowed to add the two equal one-direction numbers, which is the same as multiplying by 2.

Answer: ≈ 63 GB/s one direction, ≈ 126 GB/s aggregate.

Recall Verify

$32\times 128/130\times 16/8=63.02$ GB/s ✓ (rounds to 63); aggregate $=126.03$ GB/s ✓ (rounds to 126).

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Example 8 — Cell H: real-world word problem (will the SSD saturate the slot?)

Forecast: Gen 3 x4 is a quarter of the x16 (15.75 GB/s) → about 3.9 GB/s ≈ 3,900 MB/s. The drive wants 7,000. Expect a bottleneck.

Step 1 — slot's one-direction usable rate. $4\times 8\times \frac{128}{130}=31.508\text{ Gb/s}$ Why this step? Reads flow in one direction; we compare against the drive's read spec, so one-direction is the fair comparison.

Step 2 — to MB/s. $\frac{31.508\text{ Gb/s}}{8}=3.9385\text{ GB/s}=3,938.5\text{ MB/s}$ Why this step? Drive spec is in MB/s, so convert to matching units. Never compare Gb/s against MB/s.

Step 3 — compare. Drive wants $7,000$ MB/s; slot delivers $\approx 3,938$ MB/s. Since $3,938<7,000$, the slot is the bottleneck — the drive can only run at about 56% of its rating here. Why this step? A chain runs at the speed of its slowest link. The final decision the question asks for — "does the slot bottleneck?" — can only be answered by directly comparing the two rates in the same units, which is exactly what this step does. Whichever number is smaller is the ceiling.

Answer: Yes — the Gen 3 x4 slot caps the drive at ~3,938 MB/s. To hit 7,000 MB/s you need Gen 4 x4 (double the rate → ~7,877 MB/s).

Recall Verify

$4\times 8\times 128/130/8=3.9385$ GB/s = 3938.5 MB/s $<7000$ ✓; Gen 4 x4 doubles to $7877$ MB/s $>7000$ ✓.

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Example 9 — Cell I: exam twist — PAM-4 SNR penalty (Gen 6)

Forecast: (a) Four levels = 2 bits (${\log }_{2}4$). (b) The gaps between levels shrink to a third, and dB uses $20{\log }_{10}$ of a voltage ratio, so expect roughly $20{\log }_{10}(3)\approx 9.5$ dB.

Step 1 — (a) bits per symbol. $b={\log }_2(4)=2\text{ bits/symbol}$ Why this step? Each symbol chooses among $4$ levels; the number of bits it encodes is ${\log }_2(\text{number of levels})$. This is why PAM-4 doubles data without raising the symbol clock.

What this figure shows (Figure 3 — NRZ vs PAM-4 voltage levels). Two "eye" pictures sit side by side over the same voltage axis. Left (NRZ): just two lavender levels drawn as solid lines, $+V$ meaning bit 1 and $-V$ meaning bit 0, with a fat coral double-arrow marking the gap of $2V$ between them — a receiver can easily tell them apart even with noise. Right (PAM-4): four mint levels drawn as dashed lines ($-3V,-V,+V,+3V$) crammed into the same outer span, each pair carrying two bits ($00,01,10,11$). Every level is text-labelled with its voltage and bit-pair so colour is never required to read it. The coral double-arrow now marks a gap of only $\frac{2V}{3}$ between neighbouring levels. That is the whole story: three-times-narrower gaps mean noise that was harmless for NRZ can now flip a symbol, which is why Gen 6 must add error correction.

Step 2 — (b) voltage separation shrinks by a factor of 3. In NRZ the two levels are $2V$ apart. In PAM-4 the four levels span the same outer range but sit in three equal steps, so neighbouring levels are only $\frac{2V}{3}$ apart — a factor of $3$ closer. Why this step? The signal-to-noise margin is governed by how far apart the levels you must distinguish are. Levels that are 3× closer give you 3× less voltage headroom against noise, so the margin worsens by exactly that factor of 3.

Step 3 — convert the factor-of-3 to decibels. Decibels for a voltage/amplitude ratio use $20{\log }_{10}$: $\text{penalty}=20{\log }_{10}(3)=9.542\text{ dB}$ Why this step? dB is the standard engineering unit for signal ratios, so the exam wants the answer in dB. The multiplier is $20$ (not $10$) because signal power scales as amplitude squared, and $10{\log }_{10}(V^2)=20{\log }_{10}(V)$ — so an amplitude ratio of 3 becomes $20{\log }_{10}(3)$ dB.

Answer: (a) 2 bits/symbol; (b) about 9.5 dB worse SNR — which is exactly why Gen 6 makes forward error correction (FEC) mandatory.

Recall Verify

${\log }_{2}4=2$ ✓; $20{\log }_{10}3=9.542$ dB ✓ (rounds to the parent note's "≈ 9.5 dB").

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Recall gauntlet

Recall Which knob changed from Gen 1 to Gen 2?

Only the rate (2.5 → 5.0 GT/s). Encoding stayed 8b/10b, so throughput exactly doubled.

Recall "13× less waste" — what is actually 13×?

The wasted fraction shrank 13× ($20\%\to 1.54\%$). The usable data only grew 1.23× ($80\%\to 98.46\%$).

Recall Gen 3 x16 one-direction bandwidth?

$8\times \frac{128}{130}\times 16/8\approx 15.75$ GB/s.

Recall What is a FLIT and why is its efficiency 94.53%?

A FLIT is Gen 6's fixed 256-byte flow-control block; only 242 of those bytes are payload (the rest is FEC + CRC), so $242/256\approx 94.53\%$.

Recall Why does full-duplex let you multiply by 2?

TX and RX are separate physical pairs, so both run at full speed at once — nothing is shared, so adding them is legitimate.

Recall Why does PAM-4 need FEC when NRZ did not?

Four levels sit ~3× closer together → ~9.5 dB worse SNR margin → far more bit errors → FEC becomes mandatory to clean them up.