Exercises — PCI Express (PCIe) architecture and generations

What we're recalling: the physical make-up of one lane. A lane has two differential pairs:

• one pair for transmit (TX)
• one pair for receive (RX)

Because TX and RX are physically separate, a lane is full-duplex: it sends and receives at the same time with no turn-around delay. Two pairs = 4 wires total.

The rate doubles every generation, so this is just powers of 2 starting from 2.5:

(Gen 2 = 5, Gen 4 = 16 fill the gaps.) Notice Gen 3 breaks the exact-double pattern slightly: $5\to 8$ instead of $5\to 10$, because Gen 3 also changed the encoding, which recovered enough efficiency that a smaller rate bump still increased usable bandwidth.

Move A, then divide by 8: $BW=\frac{1\times 2.5\times 0.80}{8}\text{GB/s}=\frac{2.0}{8}=0.25\text{GB/s}=250\text{MB/s}$ What each step did: $2.5\times 0.80$ throws away the 20% overhead of 8b/10b, leaving 2.0 Gb/s of real data. Dividing by 8 converts to bytes → 0.25 GB/s = 250 MB/s. This is the famous "Gen 1 x1 = 250 MB/s" figure.

Efficiency first. 128b/130b means every 130 bits on the wire carry 128 real bits: $E=\frac{128}{130}=0.98462$ Move A: $BW=\frac{1\times 8\times 0.98462}{8}=0.98462\text{GB/s}\approx 985\text{MB/s}$ What it looks like: almost the whole wire is data now — the two sync bits per 130 are a tiny sliver (see figure s01, right bar).

Move A + Move B. $B{W}_{\text{per dir}}=\frac{16\times 8\times \frac{128}{130}}{8}=\frac{16\times 8\times 0.98462}{8}$ The $16$ and the $8$-raw times... let's just march: $=16\times 0.98462=15.75\text{GB/s (per direction)}$ (Because $\frac{8}{8}=1$, the per-lane figure is exactly the efficiency in GB/s, then times 16 lanes.) Bidirectional: $15.75\times 2=31.5\text{GB/s}$. Why the ×2 is separate: the 15.75 already used both the TX-and-RX wires? No — each lane's 15.75/16 = 0.985 GB/s is one direction only. TX and RX run simultaneously on different pairs, so the true aggregate the link can move is double.

Overhead (wasted fraction) each way: ${\text{Overhead}}_{8b/10b}=\frac{10-8}{10}=20\%{\text{Overhead}}_{128b/130b}=\frac{130-128}{130}=1.538\%$ Waste-reduction ratio (how much smaller the wasted slice got): $\frac{20\%}{1.538\%}\approx 13.0\times$ Usable-efficiency ratio (how much more data actually gets through, per lane, from encoding alone): $\frac{98.46\%}{80\%}\approx 1.23\times$ Why they differ: the wasted part shrank 13×, but since 80% was already usable, the usable part could only climb from 80% to 98.46% — a modest 1.23× gain. There isn't room for a 13× data increase because you can never exceed 100% usable.

Same encoding, so compare $L\times R$. $\text{x8 Gen 4: }\frac{8\times 16\times 0.98462}{8}=8\times 2\times 0.98462=15.75\text{GB/s}$ $\text{x16 Gen 3: }\frac{16\times 8\times 0.98462}{8}=16\times 1\times 0.98462=15.75\text{GB/s}$ They match — the claim is TRUE. Why this works: in the master formula the product $L\times R$ is what matters (efficiency and ÷8 are shared). Halving lanes ($16\to 8$) but doubling rate ($8\to 16$) leaves $L\times R$ unchanged: $128$ in both cases. This is the general rule "each generation lets you halve the lane count for the same bandwidth."

Part 1 — same line, two descriptions. A baud is one symbol per second. A transfer here is one bit-equivalent. PAM-4 sends 2 bits per symbol, so: $32\text{Gbaud}\times 2\frac{\text{bits}}{\text{symbol}}=64\text{Gbit-equivalents/s}=64\text{GT/s}$ The "64 GT/s" figure has already folded in the 2-bits/symbol; you do not multiply by 2 again.

Part 2 — FLIT efficiency. A FLIT block is 256 bytes on the wire but only 242 are useful payload: $E=\frac{242}{256}=0.94531$ Move A + Move B (per direction): $BW=\frac{16\times 64\times 0.94531}{8}=\frac{16\times 64\times 0.94531}{8}$ $=16\times 8\times 0.94531=128\times 0.94531=121.0\text{GB/s (per direction)}$ Bidirectional aggregate: $121.0\times 2=242\text{GB/s}$ — matching the spec headline figure (which quotes the bidirectional number).

Why decibels, why this ratio: a receiver's ability to tell levels apart scales with the voltage gap between them. Halving—or here, thirding—the gap makes noise three times as likely to push a symbol into the wrong level. Engineers measure such ratios logarithmically in decibels; for a voltage ratio the formula is $20{\log }_{10}(\cdot )$.

The gap ratio: $\frac{{\text{gap}}_{NRZ}}{{\text{gap}}_{PAM4}}=\frac{2V}{2V/3}=3$ SNR penalty: $20{\log }_{10}(3)=20\times 0.4771=9.54\text{dB}$ Why FEC becomes mandatory: losing ~9.5 dB of margin means far more raw symbol errors, so PAM-4 links can no longer rely on retransmission alone to stay reliable — forward error correction repairs errors in place before they force costly retries, keeping latency and throughput sane.

True per-direction ceiling (Move A + Move B, FLIT efficiency $242/256$): $BW=\frac{4\times 64\times 0.94531}{8}=4\times 8\times 0.94531=32\times 0.94531=30.25\text{GB/s}$ So a sequential read (one direction) tops out near 30.25 GB/s, not 60. The likely mis-count: $30.25\times 2\approx 60.5$ GB/s — the vendor quoted the bidirectional aggregate (TX + RX summed) as if it were a read speed. Why it's misleading: a read pulls data in one direction; the reverse path carries only tiny acknowledgements, so its bandwidth doesn't help sequential reads. Fix / reviewer's point: headline "×2" numbers are aggregate, not achievable one-way throughput.

x16 Gen 3 per-direction bandwidth ::: 15.75 GB/s Gen 1 x1 per-direction bandwidth ::: 250 MB/s Efficiency of 128b/130b ::: 128/130 ≈ 98.46% Efficiency of FLIT 242/256 ::: ≈ 94.53% Waste-reduction ratio Gen2→Gen3 ::: ≈ 13× (of the wasted fraction only) Usable-efficiency ratio Gen2→Gen3 ::: ≈ 1.23× PAM-4 SNR penalty vs NRZ ::: ≈ 9.54 dB x4 Gen 6 per-direction ceiling ::: ≈ 30.25 GB/s