PCI Express (PCIe) architecture and generations: Visual walkthrough

This page builds the effective bandwidth of a PCIe link from absolute zero. We start with two wires and a wiggling voltage, and end with the famous number "x16 Gen 3 = 15.75 GB/s per direction". Every symbol is earned before it is used. Read it top to bottom; each step has a picture that carries the idea.

Parent topic: PCI Express (PCIe) architecture and generations.

Step 1 — One lane is two tiny wire-pairs

WHAT. The smallest unit of PCIe is a lane. A lane is four wires: two carry data out (the transmit pair, TX), two carry data in (the receive pair, RX).

WHY two wires per direction and not one? A single wire measures voltage against a shared ground. Any electrical noise nearby pushes that voltage up or down and the receiver is fooled. Instead PCIe sends the same signal on two wires but flipped in sign — this is differential signalling. The receiver looks only at the difference between the two wires.

$wire A V_{+} - wire B V_{-} = what the receiver keeps V_{signal}$

Here $V_{+}$ is the voltage on wire A, $V_{-}$ is the voltage on wire B, and the difference is the real signal. If noise adds the same amount $n$ to both wires, it cancels: $(V_{+} + n) - (V_{-} + n) = V_{+} - V_{-}$ . The noise vanishes.

PICTURE. The red and teal traces are the two wires; the noise bump hits both equally, so the plum "difference" line stays clean.

Figure — PCI Express (PCIe) architecture and generations

Step 2 — Voltage wiggles become bits: the raw pulse rate

WHAT. The transmitter flips the differential voltage between "high" and "low". Each flip is a chance to send one bit. The number of these chances per second is the transfer rate, measured in GT/s (gigatransfers per second) — billions of signalling opportunities per second.

WHY call it "transfers" and not "bits"? Because — as we will see in Step 6 — for the early generations one transfer really is one raw bit, but the encoding steals some of those bits. Keeping the name "transfer" reminds us: this is the line rate, not yet the data rate.

For PCIe Gen 3, one lane runs at

$R = 8 GT/s$

where $R$ is the raw per-lane transfer rate. That is $8 \times 1 0^{9}$ voltage decisions every second, in each direction.

PICTURE. A square wave: each shaded slot is one "transfer" — one opportunity to be a 1 or a 0. Count the slots per second and you have $R$ .

Step 3 — Not every bit is yours: the encoding tax

WHAT. The raw stream cannot be pure data. The receiver has no separate clock wire; it must recover timing from the data itself. So PCIe pads the stream with extra bits. From Gen 3 onward the scheme is 128b/130b: for every 128 of your data bits, 2 housekeeping bits are inserted, making a 130-bit block.

WHY these extra 2 bits? They mark where each block begins and guarantee the voltage keeps flipping often enough for the receiver to stay locked. Without them, a long run of identical bits would leave the receiver "lost in the dark" with no edges to time against.

We define the encoding efficiency $E$ = fraction of the line that is actually your data:

$E = your bits \div total bits \frac{128}{130} = 0.9846 = 98.46%$

Here $128$ is your payload bits and $130$ is the total bits actually sent. So $1.54%$ of the line is "tax".

PICTURE. A bar of 130 slots: 128 orange "your data" slots, 2 plum "sync" slots. The tax is the thin plum sliver.

Step 4 — One lane, one direction: multiply rate by efficiency

WHAT. Now combine Steps 2 and 3. The useful data rate on one lane, one direction is the raw rate $R$ times the efficiency $E$ :

$B W_{lane} = raw GT/s R \times fraction usable E = 8 \times 0.9846 = 7.877 Gb/s$

$R = 8$ is the raw transfer rate (Step 2), $E = 0.9846$ is the usable fraction (Step 3), and the result $7.877$ is in gigabits per second (Gb/s), because each transfer here is one bit.

WHY multiply? Rate says "how many bits per second cross the wire"; efficiency says "what fraction of them are yours". Fraction-of-a-rate is a multiplication — exactly like "60 mph for $0.9$ of the trip".

PICTURE. A funnel: 8 Gb/s pours in the top, the 1.54% tax spills out the side, 7.877 Gb/s of pure data drips out the bottom.

Step 5 — Stack the lanes: multiply by the link width

WHAT. A link bundles several identical lanes side by side. The number of lanes is the link width, written $L$ = x1, x2, x4, x8, or x16 (the widest standard). Because each lane is fully independent, their data rates simply add:

$B W_{oneway} = lanes L \times per-lane Gb/s B W_{lane} = 16 \times 7.877 = 126.0 Gb/s$

$L = 16$ is the number of parallel lanes, and $B W_{lane} = 7.877$ Gb/s is the single-lane result from Step 4.

WHY add, not something cleverer? There is no shared clock and no arbitration between lanes at this level — 16 independent pipes each moving 7.877 Gb/s move $16 \times 7.877$ Gb/s together. Plain addition.

PICTURE. Sixteen parallel pipes, each labelled 7.877 Gb/s, merging into one thick pipe labelled 126 Gb/s.

Step 6 — Bits to bytes, and the two-directions question

WHAT. Data storage is measured in bytes, and 1 byte = 8 bits. Convert:

$B W_{oneway} = \frac{126.0 Gb/s}{8 bits/byte} = 15.75 GB/s (per direction)$

Notice the case-sensitive units: Gb/s is gigabits, GB/s is gigabytes — off by a factor of 8. This is the famous x16 Gen 3 = 15.75 GB/s number.

The two-directions subtlety. Because the link is full-duplex (Step 1), the same 15.75 GB/s flows the other way at the same time. The aggregate is therefore:

$B W_{aggregate} = 2 \times 15.75 = 31.5 GB/s$

PICTURE. A two-way street: 15.75 GB/s northbound, 15.75 GB/s southbound, the sign at the junction reading "31.5 GB/s total".

Step 7 — The degenerate and edge cases

Every scenario the reader might hit, so nothing surprises them.

x1 link ( $L = 1$ ). The formula still holds: $1 \times 7.877/8 = 0.985$ GB/s ≈ 985 MB/s per direction. This is the smallest real link.
The x32 "ghost". The spec defines x32 on paper, but no hardware ships it. Do not use $L = 32$ in real calculations.
Gen 1 / Gen 2 (8b/10b). Here $E = 0.80$ and one transfer is still one raw bit, so Gen 1 x1 = $2.5 \times 0.80/8 = 0.25$ GB/s = 250 MB/s. Same formula, different $E$ and $R$ .
Gen 6 (PAM-4). The rules bend: instead of two voltage levels, PAM-4 uses four levels ( ${- 3 V, - V, + V, + 3 V}$ ), so each symbol carries $lo g_{2} 4 = 2$ bits. The "64 GT/s" figure already folds this doubling in, and the efficiency uses FLIT framing ( $242/256 = 94.53%$ ). The shape of our derivation survives — only $R$ and $E$ change.

PICTURE. A small table-figure: three eye-diagrams side by side — NRZ (2 levels, wide open eye), PAM-4 (4 levels, three cramped eyes), showing why PAM-4 needs error correction (its voltage gaps are $1/3$ as tall).

The one-picture summary

The whole derivation is a chain of multiply-and-convert: raw rate → keep only your fraction → stack the lanes → convert to bytes → double for full-duplex.

$B W_{oneway} = \frac{L \times R \times E}{8} B W_{aggregate} = 2 \times B W_{oneway}$

Recall Feynman retelling — say it to a friend with no notation

Imagine one pipe that can push 8 billion pulses a second down the wire. But you can't use all of them — about 1 in 65 pulses is a little "timing marker" so the other end knows where it is, so only 98.46% of the pulses are your actual data. That leaves about 7.877 billion useful bits a second in one pipe. A big graphics-card slot bundles 16 of those pipes side by side, so multiply by 16 → 126 billion bits a second. Computer people count in bytes, and 8 bits make a byte, so divide by 8 → about 15.75 billion bytes a second going one way. And since data can flow both ways at once, if you add up both directions you get double, 31.5. The magic formula is just: rate, times the useful fraction, times how many pipes, divided by 8 — and double it if you're counting both directions. Every fancier generation only changes the "8 billion" and the "useful fraction"; the recipe never changes.

Reveal-me checks:

What does the "GT/s" (transfers/second) figure measure — data bits or raw line pulses?

Raw line pulses (signalling opportunities); the encoding tax has not yet been removed.

Why divide by 8 near the end?

To convert from bits (Gb/s) to bytes (GB/s), since 1 byte = 8 bits.

For x16 Gen 3, what is the per-direction bandwidth?

15.75 GB/s (and 31.5 GB/s aggregate for both directions).

Does going 8b/10b → 128b/130b give 13× more data?

No — it gives about 1.23× more usable data; the 13× is only the shrink in the wasted fraction.