Visual walkthrough — PCI Express (PCIe) architecture and generations

6.3.2 · D2 · Hardware › Interconnects, Buses & SoC › PCI Express (PCIe) architecture and generations

Yeh page ek PCIe link ki effective bandwidth ko bilkul scratch se build karta hai. Hum do wires aur ek wiggling voltage se shuru karte hain, aur famous number "x16 Gen 3 = 15.75 GB/s per direction" tak pahunchte hain. Har symbol ko use karne se pehle earn kiya gaya hai. Upar se neeche padho; har step mein ek picture hai jo idea carry karti hai.

Parent topic: PCI Express (PCIe) architecture and generations.

Step 1 — Ek lane do choti wire-pairs hoti hai

KYA. PCIe ki sabse choti unit ek lane hai. Ek lane mein chaar wires hote hain: do data bahar bhejte hain (transmit pair, TX), aur do data andar laate hain (receive pair, RX).

KYO do wires per direction, ek kyun nahi? Ek akeli wire voltage ko ek shared ground ke against measure karti hai. Aas-paas ka koi bhi electrical noise us voltage ko upar ya neeche push karta hai aur receiver dhoka kha jaata hai. Isliye PCIe same signal do wires par bhejta hai lekin sign flip karke — ise differential signalling kehte hain. Receiver sirf do wires ke beech ka difference dekhta hai.

$\underset{\text{wire A}}{\underbrace{V_{+}}}-\underset{\text{wire B}}{\underbrace{V_{-}}}=\underset{\text{jo receiver rakhta hai}}{\underbrace{V_{\text{signal}}}}$

Yahan $V_{+}$ wire A ka voltage hai, $V_{-}$ wire B ka voltage hai, aur unka difference real signal hai. Agar noise dono wires mein same amount $n$ add kare, toh cancel ho jaata hai: $(V_{+}+n)-(V_{-}+n)=V_{+}-V_{-}$. Noise gayab ho jaata hai.

PICTURE. Red aur teal traces do wires hain; noise bump dono ko equally hit karta hai, isliye plum "difference" line clean rehti hai.

Step 2 — Voltage wiggles se bits bante hain: raw pulse rate

KYA. Transmitter differential voltage ko "high" aur "low" ke beech flip karta hai. Har flip ek bit bhejne ka mauka hai. Yeh maukey har second kitni baar milte hain isko transfer rate kehte hain, jo GT/s mein measure hoti hai (gigatransfers per second) — har second billions of signalling opportunities.

KYO ise "transfers" bolte hain, "bits" kyun nahi? Kyunki — jaise hum Step 6 mein dekhenge — early generations mein ek transfer actually ek raw bit hota hai, lekin encoding kuch bits chura leti hai. "Transfer" naam rakhne se yaad rehta hai: yeh line rate hai, data rate abhi nahi.

PCIe Gen 3 ke liye, ek lane itni speed par run karta hai:

$R=8\text{GT/s}$

jahan $R$ raw per-lane transfer rate hai. Yeh $8\times 10^9$ voltage decisions har second hain, har direction mein.

PICTURE. Ek square wave: har shaded slot ek "transfer" hai — ek 1 ya 0 hone ka mauka. Slots per second gino toh $R$ milta hai.

Step 3 — Har bit tumhara nahi: encoding tax

KYA. Raw stream pure data nahi ho sakti. Receiver ke paas koi alag clock wire nahi hoti; use timing data se hi recover karni hoti hai. Toh PCIe stream mein extra bits add karta hai. Gen 3 se aage ka scheme 128b/130b hai: tumhare har 128 data bits ke liye, 2 housekeeping bits insert hote hain, jo ek 130-bit block banate hain.

KYO yeh extra 2 bits? Yeh mark karte hain ki har block kahan se shuru hota hai aur guarantee karte hain ki voltage itni baar flip hoti rahe ki receiver locked rahe. Inke bina, identical bits ki lambi run receiver ko "andheron mein kho" deti — koi edges nahi jiske against time kare.

Hum encoding efficiency $E$ define karte hain = line ka woh fraction jo actually tumhara data hai:

$E=\underset{\begin{array}{c}\text{tumhare bits}\\ ÷\text{kul bits}\end{array}}{\underbrace{\frac{128}{130}}}=0.9846=98.46\%$

Yahan $128$ tumhare payload bits hain aur $130$ kul bits hain jo actually bheje gaye. Toh line ka $1.54\%$ "tax" hai.

PICTURE. 130 slots ki ek bar: 128 orange "tumhara data" slots, 2 plum "sync" slots. Tax woh patli plum sliver hai.

Step 4 — Ek lane, ek direction: rate ko efficiency se multiply karo

KYA. Ab Step 2 aur 3 combine karo. Ek lane, ek direction par useful data rate raw rate $R$ times efficiency $E$ hoti hai:

$B{W}_{\text{lane}}=\underset{\text{raw GT/s}}{\underbrace{R}}\times \underset{\text{usable fraction}}{\underbrace{E}}=8\times 0.9846=7.877\text{Gb/s}$

$R=8$ raw transfer rate hai (Step 2), $E=0.9846$ usable fraction hai (Step 3), aur result $7.877$ gigabits per second (Gb/s) mein hai, kyunki yahan har transfer ek bit hai.

KYO multiply? Rate kehti hai "har second kitne bits wire cross karte hain"; efficiency kehti hai "unka kitna fraction tumhara hai". Fraction-of-a-rate ek multiplication hai — bilkul "60 mph $0.9$ part of the trip ke liye" ki tarah.

PICTURE. Ek funnel: 8 Gb/s upar se daalta hai, 1.54% tax side se nikalti hai, 7.877 Gb/s pure data neeche se tapakta hai.

Step 5 — Lanes stack karo: link width se multiply karo

KYA. Ek link kaafi identical lanes ko side by side bundle karta hai. Lanes ki sankhya link width hai, jo $L$ = x1, x2, x4, x8, ya x16 (sabse wide standard) likhte hain. Kyunki har lane fully independent hai, unki data rates simply add hoti hain:

$B{W}_{\text{oneway}}=\underset{\text{lanes}}{\underbrace{L}}\times \underset{\text{per-lane Gb/s}}{\underbrace{B{W}_{\text{lane}}}}=16\times 7.877=126.0\text{Gb/s}$

$L=16$ parallel lanes ki sankhya hai, aur $B{W}_{\text{lane}}=7.877$ Gb/s Step 4 ka single-lane result hai.

KYO add, kuch aur clever kyun nahi? Is level par lanes ke beech koi shared clock nahi hai aur koi arbitration nahi — 16 independent pipes har ek 7.877 Gb/s move karte hue $16\times 7.877$ Gb/s saath move karte hain. Simple addition.

PICTURE. Solah parallel pipes, har ek par 7.877 Gb/s likha hua, ek mote pipe mein merge hote hue jis par 126 Gb/s likha hai.

Step 6 — Bits se bytes, aur do-direction ka sawaal

KYA. Data storage bytes mein measure hoti hai, aur 1 byte = 8 bits. Convert karo:

$B{W}_{\text{oneway}}=\frac{126.0\text{Gb/s}}{8\text{bits/byte}}=15.75\text{GB/s (per direction)}$

Case-sensitive units notice karo: Gb/s gigabits hai, GB/s gigabytes hai — 8 ka factor ka fark. Yeh famous x16 Gen 3 = 15.75 GB/s number hai.

Do-direction ki subtlety. Kyunki link full-duplex hai (Step 1), same 15.75 GB/s usi waqt doosri taraf bhi flow karti hai. Isliye aggregate hai:

$B{W}_{\text{aggregate}}=2\times 15.75=31.5\text{GB/s}$

PICTURE. Ek do-taraf ki sadak: 15.75 GB/s northbound, 15.75 GB/s southbound, junction par sign "31.5 GB/s total" likha hua.

Step 7 — Degenerate aur edge cases

Har woh scenario jo reader ko mil sakta hai, taaki kuch surprise na kare.

• x1 link ($L=1$). Formula abhi bhi kaam karta hai: $1\times 7.877/8=0.985$ GB/s ≈ 985 MB/s per direction. Yeh sabse chota real link hai.
• x32 "ghost". Spec paper par x32 define karta hai, lekin koi hardware ship nahi hota. Real calculations mein $L=32$ use mat karo.
• Gen 1 / Gen 2 (8b/10b). Yahan $E=0.80$ hai aur ek transfer abhi bhi ek raw bit hai, toh Gen 1 x1 = $2.5\times 0.80/8=0.25$ GB/s = 250 MB/s. Same formula, alag $E$ aur $R$.
• Gen 6 (PAM-4). Rules thoda bend hote hain: do voltage levels ki jagah, PAM-4 chaar levels use karta hai ($\{-3V,-V,+V,+3V\}$), toh har symbol ${\log }_{2}4=2$ bits carry karta hai. "64 GT/s" figure mein yeh doubling pehle se fold in hai, aur efficiency FLIT framing use karti hai ($242/256=94.53\%$). Hamari derivation ki shape survive karti hai — sirf $R$ aur $E$ change hote hain.

PICTURE. Ek chota table-figure: teen eye-diagrams side by side — NRZ (2 levels, wide open eye), PAM-4 (4 levels, teen cramped eyes), yeh dikhate hue ki PAM-4 ko error correction kyun chahiye (uske voltage gaps $1/3$ as tall hain).

Ek-picture summary

Poori derivation multiply-and-convert ki ek chain hai: raw rate → sirf apna fraction rakho → lanes stack karo → bytes mein convert karo → full-duplex ke liye double karo.

$\boxed{B{W}_{\text{oneway}}=\frac{L\times R\times E}{8}}\boxed{B{W}_{\text{aggregate}}=2\times B{W}_{\text{oneway}}}$

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