PCI Express (PCIe) architecture and generations: Question bank

This page hunts down the misconceptions around PCI Express. Each item is a one-line reveal: read the prompt, commit to an answer in your head, then check the reasoning. The goal is not to compute — it is to catch the wrong mental picture before it hardens.

Before we start, one shared picture (see figure below): a PCIe lane is two tiny two-wire cables side by side. One cable carries data out (TX, transmit), one carries data in (RX, receive). Both work at the same time. Hold that image — most traps below come from forgetting one half of it.

Figure — PCI Express (PCIe) architecture and generations

Definition Acronyms and terms used on this page (build these first)

Every symbol below is earned before it appears in a question.

GT/s = gigatransfers per second = how many signal symbols cross a wire each second, in billions. It counts transfers, not bits — how many bits each transfer carries depends on the encoding.
baud rate = symbols per second (the same idea as GT/s). Distinguish it from bit rate = bits per second. If each symbol carries 1 bit, they're equal; if a symbol carries 2 bits, bit rate is double the baud rate.
TLP = Transaction Layer Packet = the unit PCIe sends (header + data + checksum).
CRC = Cyclic Redundancy Check = extra check-bits computed from a message so the receiver can detect corruption. CRC-32 is a CRC producing a 32-bit check value.
LCRC = Link CRC = the CRC added by the Data Link Layer for one hop between two devices.
FEC = Forward Error Correction = extra bits that let the receiver repair small errors on its own, without asking for a resend.
FLIT = flow-control unit = a fixed-size block (256 bytes in Gen 6) carrying data plus its own CRC and FEC.
PAM-4 = Pulse-Amplitude Modulation, 4 levels = a signaling scheme using 4 distinct voltage levels so each symbol carries 2 bits instead of 1.
NRZ = Non-Return-to-Zero = the simpler 2-level scheme (1 bit per symbol) used by Gens 1–5.

True or false — justify

TF1. A PCIe x16 link is faster than x8 only because it runs each lane at a higher clock.

False. Every lane in a link runs at the same per-lane rate; x16 is faster purely because it has 16 independent lanes carrying data in parallel, not because any lane is quicker.

TF2. "Serial" PCIe means data goes one direction at a time, unlike the old parallel PCI bus.

False. Serial refers to sending bits one-after-another on a single pair, not to direction. PCIe is full-duplex — a lane's TX and RX pairs both carry data simultaneously.

TF3. The published PCIe bandwidth numbers (e.g. 15.75 GB/s for Gen 3 x16) are the total you get combining both directions.

False. Those figures are per direction. Because PCIe is full-duplex, the bidirectional aggregate is double that number.

TF4. Doubling the generation number always doubles the raw signaling rate (in GT/s, gigatransfers per second).

Roughly true in GT/s from Gen 1→5 (2.5→5→8→16→32... with Gen 2→3 being 5→8, not an exact double), and Gen 6 doubles effective rate via PAM-4 rather than by raising the baud rate (symbols per second). So "always doubles the raw clock" is the trap — Gen 6 keeps the baud rate and packs more bits per symbol instead.

TF5. Switching from 8b/10b to 128b/130b encoding gave Gen 3 roughly a 13× bandwidth boost per lane.

False. 13× is how much the wasted fraction shrank (20% → 1.54%). Since 80% was already usable, actual usable throughput only rose to 98.46%, about a 1.23× gain from the encoding change alone.

TF6. Differential signaling makes a lane faster.

False. Differential signaling makes a lane quieter — it rejects common-mode noise so the receiver can trust smaller, faster voltage swings. Speed is enabled, but the direct job is noise rejection, not raw speed.

TF7. PAM-4 in Gen 6 sends data twice as fast by increasing the number of symbols per second (the baud rate).

False. PAM-4 keeps the baud rate (symbols per second) fixed and encodes 2 bits per symbol instead of 1, so the same number of symbols carries twice the bits.

TF8. Forward error correction (FEC) was added in early PCIe generations to catch bit errors.

False. FEC arrives first in Gen 6, made mandatory because PAM-4's four tightly-packed voltage levels are far more error-prone. Gens 1–5 relied on CRC + ACK/NAK retry, not FEC.

TF9. A single ACK/NAK retry mechanism lives in the Transaction Layer alongside packet assembly.

False. ACK/NAK link-level retry lives in the Data Link Layer. The Transaction Layer assembles TLPs (Transaction Layer Packets) and handles flow control/ordering; separation of concerns keeps each layer's job distinct.

Spot the error

SE1. "PCIe x32 is the widest link you can buy in a modern motherboard."

Error: x16 is the widest link implemented in practice. x32 exists only on paper in the spec and was never built.

SE2. "8b/10b means 8 data bits become 10 stored bits, so efficiency is 8/10 = 80%, and 128b/130b means efficiency is 128/130 = 80% too."

Error: 128/130 ≈ 98.46%, not 80%. Only 2 sync bits per 128 data bits means almost all the line carries real data.

SE3. "Overhead for 128b/130b is (130−128)/128."

Error: overhead is measured against the total transmitted bits, so it's (130−128)/130 = 1.54%. Dividing by 128 gives the wrong denominator.

SE4. "Because PAM-4 has 4 voltage levels, its signal-to-noise requirement is 4× worse than 2-level NRZ."

Error: see the voltage-spacing figure below — the gap between adjacent levels shrinks from

2 V

(NRZ) to

2 V /3

(PAM-4), a factor of 3, giving an SNR penalty of about 9.5 dB, not a factor of 4.

Intuition Where the "3" and the "20 log₁₀" come from (SE4 unpacked)

The factor of 3: NRZ uses two levels, say $- V$ and $+ V$ , so the gap the receiver must distinguish is $2 V$ . PAM-4 must fit four levels ${- 3 V, - V, + V, + 3 V}$ into the same total swing from $- 3 V$ to $+ 3 V$ ; adjacent levels are only $2 V$ apart out of a range that now holds 3 gaps, so each usable gap is $\frac{2 V}{3}$ . Smaller gap → the noise that used to be harmless now flips a level. See the figure. The " $20 lo g_{10}$ ": signal-to-noise ratio (SNR) is a ratio of powers. Because we compare human-unwieldy ratios that span huge ranges, engineers use decibels (dB): $dB = 10 lo g_{10} (power ratio)$ . Power grows with the square of voltage ( $P \propto V^{2}$ ), so in terms of a voltage ratio, $10 lo g_{10} (V^{2}) = 20 lo g_{10} (V)$ — that is where the 20 replaces the 10. Plugging the voltage-gap ratio of 3: $20 lo g_{10} (3) \approx 9.5$ dB worse.

SE5. "The Physical Layer adds the sequence number and LCRC to guarantee delivery."

Error: sequence numbers and LCRC (Link CRC) are added by the Data Link Layer. The Physical Layer serializes bits, does encoding and differential signaling.

SE6. "CRC-32 can detect any possible error pattern with certainty."

Error: CRC-32 detects all burst errors up to 32 bits and all odd-bit errors with certainty, but only catches longer bursts with probability >99.99% — not 100%.

SE7. "A x4 device plugged into a x16 slot cannot work because the widths don't match."

Error: PCIe negotiates down. A x4 card in a x16 slot links at x4 (only 4 lanes used); wider slots accept narrower cards.

Why questions

WHY1. Why does PCIe use two separate wire pairs (TX and RX) instead of one shared pair that turns around?

A turn-around pair needs a delay to switch direction and arbitration to decide who talks. Dedicated TX and RX pairs let both directions flow at once with zero turn-around, which is what "full-duplex" buys you.

WHY2. Why did early PCIe (Gen 1–2) use the "wasteful" 8b/10b encoding instead of the efficient 128b/130b from day one?

At low speeds (2.5–5 GT/s, gigatransfers per second) the frequent bit transitions of 8b/10b gave the receiver reliable clock recovery cheaply. The extra complexity of 128b/130b plus scrambling only paid off once speeds hit 8 GT/s.

WHY3. Why is the CRC appended as a remainder after dividing the message by a fixed generator polynomial, rather than using a simple bit-count?

A message is treated as a big binary number; dividing it means every message bit affects the quotient and therefore the remainder, so flipping any single bit changes that remainder. A plain bit-count (parity) only tracks whether the total is odd or even, so it silently misses any even number of errors. See the worked long-division figure below.

WHY4. Why did Gen 6 need FEC (Forward Error Correction) when Gens 1–5 got away with only CRC + retry?

PAM-4 squeezes 4 voltage levels into the same range, so errors are frequent enough that retrying every corrupted packet would waste huge bandwidth. FEC fixes many errors in-place without a round-trip retry.

WHY5. Why does adding lanes not reduce the per-lane latency of a single transfer?

Lanes add width (more bits in parallel), not speed on any single path. A given byte still travels one lane at that lane's rate; more lanes help throughput, not one packet's crossing time.

WHY6. Why is the "13× less waste" figure technically true yet misleading?

It's a ratio of wasted fractions (20% vs 1.54%), which is honest. It's misleading because 80% was already usable, so real data throughput only climbs ~1.23×, not 13×.

WHY7. Why split PCIe into Transaction, Data Link, and Physical layers instead of one monolithic protocol?

Separation of concerns: the Transaction Layer reasons about logical transfers, the Data Link Layer guarantees reliable delivery over one hop, and the Physical Layer handles electrical detail. Each can evolve (e.g. new encoding) without rewriting the others.

Edge cases

EC1. What is the effective bandwidth of a PCIe link with zero active lanes (a fully unlinked slot)?

Zero — with no trained lanes there is no data path at all. Link training must bring up at least x1 before any TLP (Transaction Layer Packet) moves.

EC2. If a x16 link trains down to x1 because 15 lanes fail signal integrity, does it still function?

Yes, but at 1/16 the throughput. PCIe degrades gracefully to the widest reliably-trainable width; correctness holds, bandwidth drops.

EC3. In FLIT mode (Gen 6, 242 useful bytes per 256-byte block), what happens to the efficiency compared to 128b/130b?

Efficiency drops slightly to about 242/256 ≈ 94.53%, because the FLIT block reserves more bytes (for CRC and FEC) than the 2 sync bits of 128b/130b — the cost of surviving PAM-4's error-prone channel.

EC4. What does a NAK from the Data Link Layer cause, and does the Transaction Layer notice?

A NAK triggers retransmission of the affected TLP from a replay buffer at the Data Link Layer. Ideally the Transaction Layer never sees it — reliable delivery is the lower layer's job.

EC5. A lane's TX and RX pairs each carry bits at the same per-direction throughput — call that throughput

R

(in bits per second). Is the "lane bandwidth"

R

2 R

It depends on the convention: per-direction it is

R

, and the bidirectional aggregate (TX plus RX) is

2 R

. Spec tables quote per-direction, so always state which you mean.

EC6. A Gen 3-capable device is placed in a Gen 4-capable slot (or vice-versa). What speed do they run at, and does it still work?

They negotiate down to the highest generation both endpoints support — here Gen 3. The link works fine; it simply runs at Gen 3 rates, exactly the way width auto-negotiates in EC2 but along the speed axis instead of the lane-count axis.

EC7. A CRC check passes (zero remainder) but the message is still corrupt — is this possible?

Yes, rarely. If the error pattern happens to be an exact multiple of the generator polynomial, the remainder is zero and the error slips through — this is the <0.01% of long bursts CRC-32 misses.

Recall Fastest self-test

Answer these three in one breath each. PCIe published bandwidth is per-direction or total? ::: Per-direction; double it for bidirectional aggregate. Which layer does ACK/NAK retry? ::: The Data Link Layer. Did the Gen 3 encoding change give ~13× or ~1.23× more usable data? ::: ~1.23×; the 13× refers only to the shrinking of wasted overhead.