6.3.2 · D1Interconnects, Buses & SoC

Foundations — PCI Express (PCIe) architecture and generations

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This page builds every word, symbol, and picture the parent note leans on. Read it top to bottom — nothing below uses anything not defined above it. When you can pass the #Equipment checklist at the bottom, go read the main topic note.


1. A "bit" and a "wire that carries it"

Picture a single wire. If we agree that "low voltage = 0" and "high voltage = 1", then by watching the wire's voltage over time we can read a stream of bits.

Figure — PCI Express (PCIe) architecture and generations

Look at the blue line in the figure: each flat section is one bit-slot. Where the line is low it means 0, where it is high it means 1. Reading left to right gives 0 1 1 0 1. The width of each slot is the bit period — how long each bit is "held" on the wire.


2. Rate: bits per second, and "transfers"

Why a new word "transfer" instead of just "bits"? Because — as we'll see in Section 6 — not every slot on the wire carries a useful data bit; some slots are used for housekeeping. "GT/s" honestly counts slots on the wire; the useful-data rate is always a bit lower.

For the older encodings, useful bits per transfer , so 8 GT/s 8 Gb/s of raw line rate.


3. The prefixes: G, b vs B

Beginners lose whole factors of 8 here, so pin it down.

Convert bits/s to bytes/s
divide by 8
63 Gb/s in bytes/s
7.875 GB/s

4. One wire is noisy — so use TWO (differential signalling)

A single wire near motors, radios, and other chips picks up stray voltage — electromagnetic interference (EMI) — random voltage bumps that can flip a 0 into a 1.

The fix is to send the signal on two wires at once: one carries the signal, the other carries its exact mirror image. The receiver looks only at the difference between them.

Figure — PCI Express (PCIe) architecture and generations

In the figure, the orange and green lines are the two wires; when noise hits (the gray wobble) it lands on both equally, so it cancels when you subtract them. The blue line at the bottom is that clean difference. This is called differential signalling, and the two wires are a differential pair.


5. A lane: two pairs, both directions at once

Figure — PCI Express (PCIe) architecture and generations

The figure shows one lane: the orange TX pair leaves the chip, the green RX pair arrives, and both are busy at the same instant. The parent note's "" for a lane comes straight from here — rate going out plus rate coming in.

Why "x16" and not "x32"? x16 is the widest link ever actually built; more lanes cost too many pins and traces to be worth it.


6. Encoding: why "8b/10b" and "128b/130b"

Now the tricky part. To read the wire correctly, the receiver must know exactly where each bit-slot starts. It figures this out by watching for voltage flips. But if the data is a long run of identical bits (say 0000000000), the wire never flips and the receiver loses its place — like counting fence-posts in fog.

Two schemes appear in the topic:

  • 8b/10b: take 8 real data bits, send 10 bits on the wire. 2 of every 10 bits are "overhead" (housekeeping, not data).
  • 128b/130b: take 128 real data bits, send 130 on the wire. Only 2 extra per 128.

ge — new symbol below — read on.


7. The maths symbols the topic borrows

The parent note uses a handful of pure-maths tools. Here is each, from zero.

Why and not ordinary division? Because information doubles every time you add one bit, and is exactly the tool that "undoes" doubling — it converts number of choices into number of bits.

Why a polynomial and not plain numbers? Because "divide and keep the remainder" catches accidental bit-flips extremely reliably, and polynomials-over-bits make that division cheap in hardware.


8. Packets and error-checking words


How these feed the topic

bit 0 or 1

rate and GT/s

differential pair

lane TX plus RX

link width x1 to x16

encoding 8b10b 128b130b

log base 2

bandwidth per generation

packet TLP

CRC ECRC LCRC

polynomial G of x

ACK NAK and FEC

PCIe architecture and generations


Equipment checklist

Cover the right side; you should be able to answer each before reading the main note.

What a bit is
The smallest unit of info: 0 or 1, shown as low/high voltage on a wire
What "8 GT/s" means
8 billion transfers (bit-slots on the wire) per second per lane
The difference between b and B
b = bit, B = byte = 8 bits; divide bit-rate by 8 for byte-rate
Why PCIe uses two wires per signal
Differential pair — noise hits both equally and cancels in the difference
What one lane contains
One TX differential pair + one RX differential pair, running full-duplex
What full-duplex means
Data flows both directions simultaneously
What x16 means
A link of 16 parallel lanes
Why encoding exists
Extra bits keep the wire flipping so the receiver stays synchronized, and keep voltage balanced
Efficiency of 8b/10b vs 128b/130b
80% vs ~98.46%
Why the encoding gain is ~1.23× not 13×
13× is the shrink in wasted fraction; usable data only rises from 80% to 98.46%
What equals and why it appears
2; it's the bits-per-symbol for 4 voltage levels (PAM-4)
What a CRC does
A check-number that detects corrupted bits by polynomial division
ACK vs NAK
ACK = received clean; NAK = corrupt, please resend
What FEC adds
Extra bits so the receiver fixes small errors without a resend (new in Gen 6)