Foundations — PCI Express (PCIe) architecture and generations

6.3.2 · D1 · Hardware › Interconnects, Buses & SoC › PCI Express (PCIe) architecture and generations

Yeh page har woh word, symbol, aur picture build karta hai jis par parent note rely karta hai. Isse upar se neeche padho — neeche jo bhi hai woh kisi aisi cheez ka use nahi karta jo usse pehle define na ki gayi ho. Jab tum neeche diye #Equipment checklist ko pass kar lo, tab the main topic note padho.

1. Ek "bit" aur "woh wire jo use carry karti hai"

Ek single wire ka picture lo. Agar hum agree karein ki "low voltage = 0" aur "high voltage = 1", toh wire ki voltage ko time ke saath dekhkar hum bits ki ek stream read kar sakte hain.

Figure mein blue line dekho: har flat section ek bit-slot hai. Jahan line low hai wahan 0 matlab hai, jahan high hai wahan 1 matlab hai. Left se right padhne par 0 1 1 0 1 milta hai. Har slot ki width bit period hai — har bit wire par kitni der "hold" hoti hai.

2. Rate: bits per second, aur "transfers"

"Bits" ki jagah "transfer" nayi word kyun? Kyunki — jaise Section 6 mein dekhenge — wire par har slot ek useful data bit carry nahi karta; kuch slots housekeeping ke liye use hote hain. "GT/s" honestly wire par slots count karta hai; useful-data rate hamesha thodi kam hoti hai.

Purane encodings ke liye, useful bits per transfer $=1$, isliye 8 GT/s $\approx$ 8 Gb/s raw line rate hai.

3. Prefixes: G, b vs B

Beginners yahan poore 8 ke factors kho dete hain, isliye ise theek se samajh lo.

4. Ek wire noisy hoti hai — toh DO use karo (differential signalling)

Motors, radios, aur doosre chips ke paas ek single wire stray voltage pickup karti hai — electromagnetic interference (EMI) — random voltage bumps jo ek 0 ko 1 mein flip kar sakte hain.

Iska fix hai signal ko ek saath do wires pe bhejna: ek signal carry karti hai, doosri uski exact mirror image. Receiver sirf unke beech ka difference dekhta hai.

Figure mein, orange aur green lines do wires hain; jab noise aati hai (gray wobble) toh woh dono par equally padti hai, isliye subtract karne par cancel ho jaati hai. Neeche blue line woh clean difference hai. Isse differential signalling kehte hain, aur do wires ek differential pair hain.

5. Ek lane: do pairs, dono directions ek saath

Figure ek lane dikhata hai: orange TX pair chip se nikalta hai, green RX pair aata hai, aur dono ek hi instant par busy hain. Parent note ka "$2R$" ek lane ke liye seedha yahan se aata hai — rate $R$ bahar jaata hai plus rate $R$ andar aata hai.

"x16" kyun na ki "x32"? x16 sabse wide link hai jo kabhi actually bani hai; zyada lanes pin aur traces mein zyada cost maangti hain, jo worth it nahi hai.

6. Encoding: "8b/10b" aur "128b/130b" kyun

Ab tricky part. Wire ko sahi se padhne ke liye, receiver ko exactly pata hona chahiye ki har bit-slot kahan shuru hota hai. Yeh voltage flips dekhkar samajhta hai. Lekin agar data mein identical bits ka lamba run ho (jaise 0000000000), toh wire kabhi flip nahi hoti aur receiver apni jagah bhool jaata hai — jaise kohre mein fence-posts count karna.

Topic mein do schemes aati hain:

• 8b/10b: 8 real data bits lo, wire par 10 bits bhejo. Har 10 mein se 2 bits "overhead" hain (housekeeping, data nahi).
• 128b/130b: 128 real data bits lo, wire par 130 bhejo. Sirf 2 extra har 128 par.

ge — naya symbol neeche — aage padho.

7. Topic jo maths symbols use karta hai

Parent note kuch pure-maths tools use karta hai. Yahan har ek, zero se.

${\log }_2$ kyun aur ordinary division kyun nahi? Kyunki information har baar double hoti hai jab ek bit add karo, aur ${\log }_2$ exactly woh tool hai jo "doubling ko undo" karta hai — yeh number of choices ko number of bits mein convert karta hai.

Polynomial kyun aur plain numbers kyun nahi? Kyunki "divide and keep the remainder" accidental bit-flips ko bahut reliably pakadta hai, aur bits-ke-upar-polynomials us division ko hardware mein sasta banate hain.

8. Packets aur error-checking words

Yeh topic ko kaise feed karte hain

Equipment checklist

Right side cover karo; main note padhne se pehle har ek ka jawab dena chahiye.