PCI Express (PCIe) architecture and generations: Question bank

6.3.2 · D5 · Hardware › Interconnects, Buses & SoC › PCI Express (PCIe) architecture and generations

Yeh page PCI Express ke baare mein jo galat-fahmiyaan hain, unhe pakadne ki koshish karta hai. Har item ek single-line reveal hai: prompt padho, apne dimag mein jawab pakko karo, phir reasoning check karo. Goal yeh nahi ki calculate karo — goal yeh hai ki galat mental picture hardened ho jaaye usse pehle pakad lo.

Shuru karne se pehle, ek shared picture dekho (neeche wala figure): ek PCIe lane do chhoti two-wire cables hain jo side by side hain. Ek cable data bahar le jaati hai (TX, transmit), ek data andar laati hai (RX, receive). Dono ek saath kaam karti hain. Yeh image apne dimaag mein rakho — neeche ke zyaadatar traps isi ko bhool jaane se aate hain.

Figure — PCI Express (PCIe) architecture and generations

Definition Is page par use kiye gaye Acronyms aur terms (pehle inhe build karo)

Neeche diya har symbol kisi question mein aane se pehle samjhaya gaya hai.

GT/s = gigatransfers per second = ek second mein ek wire par kitne signal symbols cross karte hain, billions mein. Yeh transfers count karta hai, bits nahi — har transfer mein kitne bits hain yeh encoding par depend karta hai.
baud rate = symbols per second (GT/s jaisa hi concept). Isse bit rate = bits per second se alag karo. Agar har symbol 1 bit carry kare, toh dono equal hain; agar symbol 2 bits carry kare, toh bit rate baud rate se double hogi.
TLP = Transaction Layer Packet = woh unit jo PCIe bhejta hai (header + data + checksum).
CRC = Cyclic Redundancy Check = extra check-bits jo ek message se compute ki jaati hain taaki receiver corruption detect kar sake. CRC-32 ek aisa CRC hai jo 32-bit check value produce karta hai.
LCRC = Link CRC = woh CRC jo Data Link Layer do devices ke beech ek hop ke liye add karta hai.
FEC = Forward Error Correction = extra bits jo receiver ko chhhoti errors khud repair karne dete hain, bina resend maange.
FLIT = flow-control unit = ek fixed-size block (Gen 6 mein 256 bytes) jo data ke saath apna CRC aur FEC bhi carry karta hai.
PAM-4 = Pulse-Amplitude Modulation, 4 levels = ek signaling scheme jo 4 distinct voltage levels use karta hai taaki har symbol 1 ki jagah 2 bits carry kare.
NRZ = Non-Return-to-Zero = simpler 2-level scheme (1 bit per symbol) jo Gens 1–5 use karte hain.

Sahi ya galat — justify karo

TF1. PCIe x16 link, x8 se sirf isliye faster hai kyunki woh har lane ko zyaada clock par run karta hai.

Galat. Ek link ki har lane ek hi per-lane rate par chalti hai; x16 isliye faster hai kyunki uske paas 16 independent lanes hain jo parallel mein data carry karti hain, na ki kisi lane ki speed zyaada hoti hai.

TF2. "Serial" PCIe ka matlab hai data ek time mein ek hi direction mein jaata hai, purane parallel PCI bus ke unlike.

Galat. Serial ka matlab hai bits ek single pair par ek ke baad ek bhejna, direction se koi lena-dena nahi. PCIe full-duplex hai — ek lane ke TX aur RX pairs dono ek saath data carry karte hain.

TF3. PCIe ke published bandwidth numbers (jaise Gen 3 x16 ke liye 15.75 GB/s) woh total hain jo dono directions milaakar milta hai.

Galat. Yeh figures per direction hain. Kyunki PCIe full-duplex hai, bidirectional aggregate uss number ka double hoga.

TF4. Generation number double karne par raw signaling rate (GT/s, gigatransfers per second mein) hamesha double ho jaata hai.

GT/s mein Gen 1→5 tak roughly sahi hai (2.5→5→8→16→32... lekin Gen 2→3 mein 5→8 hai, exact double nahi), aur Gen 6 baud rate badhane ki jagah PAM-4 ke through effective rate double karta hai. Toh "hamesha raw clock double karta hai" yehi trap hai — Gen 6 baud rate same rakhta hai aur har symbol mein zyaada bits pack karta hai.

TF5. 8b/10b se 128b/130b encoding switch karne se Gen 3 ko per lane roughly 13× bandwidth boost mila.

Galat. 13× woh hai jitna waste fraction hua (20% → 1.54%). Kyunki 80% pehle se usable tha, asli usable throughput sirf 98.46% tak badha, yaani encoding change se akela sirf ~1.23× gain.

TF6. Differential signaling ek lane ko faster banata hai.

Galat. Differential signaling ek lane ko quieter banata hai — yeh common-mode noise reject karta hai taaki receiver chhoti, tezi se badalne wali voltage swings par trust kar sake. Speed enable hoti hai, lekin direct kaam noise rejection hai, raw speed nahi.

TF7. Gen 6 mein PAM-4 data double speed par bhejta hai kyunki symbols per second (baud rate) badh jaata hai.

Galat. PAM-4 baud rate (symbols per second) fixed rakhta hai aur har symbol mein 1 ki jagah 2 bits encode karta hai, isliye same symbols double bits carry karte hain.

TF8. Forward error correction (FEC) early PCIe generations mein bit errors pakadne ke liye add ki gayi thi.

Galat. FEC pehli baar Gen 6 mein aata hai, mandatory banaya gaya kyunki PAM-4 ke chaar tightly-packed voltage levels bahut zyaada error-prone hain. Gens 1–5 FEC nahi, CRC + ACK/NAK retry par rely karte the.

TF9. Ek single ACK/NAK retry mechanism Transaction Layer mein packet assembly ke saath rehta hai.

Galat. ACK/NAK link-level retry Data Link Layer mein rehta hai. Transaction Layer TLPs (Transaction Layer Packets) assemble karta hai aur flow control/ordering handle karta hai; concerns ka yeh separation har layer ka kaam alag rakhta hai.

Error pakdo

SE1. "PCIe x32 sabse wide link hai jo aaj ek modern motherboard mein milti hai."

Error: x16 woh widest link hai jo practically implement hoti hai. x32 sirf spec mein paper par exist karta hai, kabhi banaya nahi gaya.

SE2. "8b/10b ka matlab hai 8 data bits become 10 stored bits, toh efficiency 8/10 = 80% hai, aur 128b/130b ka matlab hai efficiency 128/130 = 80% bhi hai."

Error: 128/130 ≈ 98.46% hai, 80% nahi. 128 data bits par sirf 2 sync bits ka matlab hai ki line par almost sab kuch real data hai.

SE3. "128b/130b ka overhead (130−128)/128 hai."

Error: overhead total transmitted bits ke against measure hota hai, toh yeh (130−128)/130 = 1.54% hai. 128 se divide karna galat denominator deta hai.

SE4. "Kyunki PAM-4 ke 4 voltage levels hain, iska signal-to-noise requirement 2-level NRZ se 4× worse hai."

Error: neeche wala voltage-spacing figure dekho — adjacent levels ke beech ka gap

2 V

(NRZ) se

2 V /3

(PAM-4) ho jaata hai, factor of 3, jisse SNR penalty roughly 9.5 dB hoti hai, 4 ka factor nahi.

Intuition "3" aur "20 log₁₀" kahan se aate hain (SE4 detail mein)

Factor of 3: NRZ do levels use karta hai, maano $- V$ aur $+ V$ , toh gap jo receiver distinguish karta hai $2 V$ hai. PAM-4 ko chaar levels ${- 3 V, - V, + V, + 3 V}$ usi total swing $- 3 V$ se $+ 3 V$ mein fit karne hote hain; adjacent levels sirf $2 V$ apart hain ek aise range mein jo ab 3 gaps rakhta hai, toh har usable gap $\frac{2 V}{3}$ hai. Chhota gap → pehle jo noise harmless thi woh ab ek level flip kar deti hai. Figure dekho. " $20 lo g_{10}$ ": signal-to-noise ratio (SNR) powers ka ratio hai. Kyunki hum aise ratios compare karte hain jo huge ranges span karte hain, engineers decibels (dB) use karte hain: $dB = 10 lo g_{10} (power ratio)$ . Power voltage ke square se badhti hai ( $P \propto V^{2}$ ), toh voltage ratio ke terms mein, $10 lo g_{10} (V^{2}) = 20 lo g_{10} (V)$ — yehi hai jahan 10 ki jagah 20 aata hai. Voltage-gap ratio of 3 daalo: $20 lo g_{10} (3) \approx 9.5$ dB worse.

SE5. "Physical Layer delivery guarantee karne ke liye sequence number aur LCRC add karta hai."

Error: sequence numbers aur LCRC (Link CRC) Data Link Layer add karta hai. Physical Layer bits serialize karta hai, encoding aur differential signaling handle karta hai.

SE6. "CRC-32 kisi bhi possible error pattern ko certainty ke saath detect kar sakta hai."

Error: CRC-32 sab burst errors up to 32 bits aur sab odd-bit errors certainty ke saath detect karta hai, lekin lambe bursts ko sirf >99.99% probability se pakadta hai — 100% nahi.

SE7. "x4 device ko x16 slot mein lagao toh kaam nahi karega kyunki widths match nahi karti."

Error: PCIe negotiate karke down aata hai. x16 slot mein x4 card x4 par link karta hai (sirf 4 lanes use hoti hain); wide slots narrow cards accept karte hain.

Why questions

WHY1. PCIe do alag wire pairs (TX aur RX) kyun use karta hai ek shared pair ki jagah jo turn around kare?

Turn-around pair ko direction switch karne ke liye delay aur yeh decide karne ke liye arbitration chahiye ki kaun bole. Dedicated TX aur RX pairs dono directions ko ek saath zero turn-around ke saath flow karne dete hain — yehi hai jo "full-duplex" khareedta hai.

WHY2. Early PCIe (Gen 1–2) ne "wasteful" 8b/10b encoding kyun use ki Gen 3 se efficient 128b/130b ki jagah?

Kam speeds par (2.5–5 GT/s, gigatransfers per second) 8b/10b ke frequent bit transitions ne receiver ko sasti clock recovery dili. 128b/130b plus scrambling ki extra complexity tabhi faydamand hui jab speeds 8 GT/s tak pahunchi.

WHY3. CRC ek simple bit-count ki jagah message ko ek fixed generator polynomial se divide karne ke baad remainder ke roop mein kyun append hota hai?

Ek message ko ek bada binary number maana jaata hai; use divide karna matlab har message bit quotient ko affect karti hai aur isliye remainder ko bhi, toh koi bhi single bit flip karna woh remainder change kar deta hai. Plain bit-count (parity) sirf track karta hai ki total odd hai ya even, toh yeh silently miss kar leta hai koi bhi even number of errors. Neeche ka worked long-division figure dekho.

WHY4. Gen 6 ko FEC (Forward Error Correction) kyun chahiye tha jab Gens 1–5 sirf CRC + retry se kaam chala lete the?

PAM-4 usi range mein 4 voltage levels squeeze karta hai, isliye errors itni frequent hoti hain ki har corrupt packet retry karna huge bandwidth waste kar deta. FEC kaafi errors in-place fix karta hai bina round-trip retry ke.

WHY5. Lanes add karne se ek single transfer ki per-lane latency kyun kam nahi hoti?

Lanes width add karte hain (parallel mein zyaada bits), kisi single path par speed nahi. Ek given byte phir bhi ek lane par usi lane ki rate se travel karta hai; zyaada lanes throughput help karte hain, ek packet ki crossing time nahi.

WHY6. "13× less waste" figure technically sahi kyun hai phir bhi misleading kyun hai?

Yeh wasted fractions ka ratio hai (20% vs 1.54%), jo honest hai. Yeh misleading isliye hai kyunki 80% pehle se usable tha, toh real data throughput sirf ~1.23× badhta hai, 13× nahi.

WHY7. PCIe ko Transaction, Data Link, aur Physical layers mein kyun split kiya — ek monolithic protocol ki jagah?

Separation of concerns: Transaction Layer logical transfers ke baare mein sochta hai, Data Link Layer ek hop par reliable delivery guarantee karta hai, aur Physical Layer electrical detail handle karta hai. Har ek evolve ho sakta hai (jaise new encoding) baaki ko rewrite kiye bina.

Edge cases

EC1. PCIe link ka effective bandwidth kya hai jisme zero active lanes hain (fully unlinked slot)?

Zero — koi trained lane nahi matlab koi data path hi nahi. Link training kam se kam x1 bring up kare tabhi koi TLP (Transaction Layer Packet) move hoga.

EC2. Agar x16 link x1 tak train down ho jaaye kyunki 15 lanes signal integrity fail kar dein, toh kya yeh phir bhi kaam karta hai?

Haan, lekin 1/16 throughput par. PCIe gracefully widest reliably-trainable width tak degrade karta hai; correctness bani rehti hai, bandwidth girti hai.

EC3. FLIT mode mein (Gen 6, 256-byte block mein 242 useful bytes), 128b/130b se compare karne par efficiency kya hoti hai?

Efficiency thodi girti hai roughly 242/256 ≈ 94.53% tak, kyunki FLIT block 128b/130b ke 2 sync bits se zyaada bytes reserve karta hai (CRC aur FEC ke liye) — PAM-4 ke error-prone channel mein survive karne ki cost.

EC4. Data Link Layer ka NAK kya cause karta hai, aur kya Transaction Layer notice karta hai?

NAK Data Link Layer par ek replay buffer se affected TLP ki retransmission trigger karta hai. Ideally Transaction Layer use kabhi nahi dekhta — reliable delivery lower layer ka kaam hai.

EC5. Ek lane ke TX aur RX pairs dono ek hi per-direction throughput par bits carry karte hain — use

R

(bits per second mein) kaho. Toh "lane bandwidth"

R

hai ya

2 R

Yeh convention par depend karta hai: per-direction yeh

R

hai, aur bidirectional aggregate (TX plus RX)

2 R

hai. Spec tables per-direction quote karte hain, toh hamesha batao kaunsa mean kar rahe ho.

EC6. Gen 3-capable device ko Gen 4-capable slot mein lagao (ya ulta). Yeh kis speed par run karenge, aur kya kaam karega?

Yeh highest generation negotiate karke down aate hain jo dono endpoints support karte hain — yahan Gen 3. Link theek kaam karta hai; sirf Gen 3 rates par run karta hai, bilkul waise hi jaise width EC2 mein auto-negotiate karti hai lekin lane-count axis ki jagah speed axis par.

EC7. CRC check pass ho jaata hai (zero remainder) lekin message phir bhi corrupt hai — kya yeh possible hai?

Haan, rarely. Agar error pattern generator polynomial ka exact multiple ho, toh remainder zero hota hai aur error slip through ho jaata hai — yahi woh <0.01% lambe bursts hain jo CRC-32 miss karta hai.

Recall Fastest self-test

Yeh teen ek ek saans mein jawab do. PCIe published bandwidth per-direction hai ya total? ::: Per-direction; bidirectional aggregate ke liye ise double karo. Kaun sa layer ACK/NAK retry karta hai? ::: Data Link Layer. Gen 3 encoding change ne ~13× ya ~1.23× zyaada usable data diya? ::: ~1.23×; 13× sirf wasted overhead ke shrinkage ko refer karta hai.