Exercises — PCI Express (PCIe) architecture and generations

Hum kya recall kar rahe hain: ek lane ki physical banawat. Ek lane mein two differential pairs hote hain:

• ek pair transmit (TX) ke liye
• ek pair receive (RX) ke liye

Kyunki TX aur RX physically alag hain, ek lane full-duplex hai: woh bina kisi turn-around delay ke ek saath bhejta aur receive karta hai. Do pairs = kul 4 wires.

Rate har generation mein double hoti hai, toh yeh sirf 2.5 se shuru hone wale powers of 2 hain:

(Gen 2 = 5, Gen 4 = 16 gaps fill karte hain.) Dhyaan do ki Gen 3 exact-double pattern se thoda alag hai: $5\to 8$ instead of $5\to 10$, kyunki Gen 3 ne encoding bhi badli, jisne itni efficiency recover ki ki ek chhota sa rate bump phir bhi usable bandwidth badhane ke liye kaafi tha.

Move A, phir 8 se divide: $BW=\frac{1\times 2.5\times 0.80}{8}\text{GB/s}=\frac{2.0}{8}=0.25\text{GB/s}=250\text{MB/s}$ Har step ne kya kiya: $2.5\times 0.80$ ne 8b/10b ke 20% overhead ko uda diya, 2.0 Gb/s real data bachata hai. 8 se divide karna bytes mein convert karta hai → 0.25 GB/s = 250 MB/s. Yeh famous "Gen 1 x1 = 250 MB/s" figure hai.

Pehle efficiency. 128b/130b ka matlab hai wire par har 130 bits mein 128 real bits hain: $E=\frac{128}{130}=0.98462$ Move A: $BW=\frac{1\times 8\times 0.98462}{8}=0.98462\text{GB/s}\approx 985\text{MB/s}$ Yeh kaisa dikhta hai: ab almost poora wire data hai — 130 mein se do sync bits ek tiny sliver hain (figure s01, right bar dekho).

Move A + Move B. $B{W}_{\text{per dir}}=\frac{16\times 8\times \frac{128}{130}}{8}=\frac{16\times 8\times 0.98462}{8}$ $16$ aur $8$-raw ko seedha chalte hain: $=16\times 0.98462=15.75\text{GB/s (per direction)}$ (Kyunki $\frac{8}{8}=1$, per-lane figure exactly efficiency GB/s mein hai, phir 16 lanes se multiply.) Bidirectional: $15.75\times 2=31.5\text{GB/s}$. Kyun ×2 alag hai: 15.75 ne already both TX-aur-RX wires use ki hain? Nahi — har lane ka 15.75/16 = 0.985 GB/s sirf ek direction hai. TX aur RX alag pairs par simultaneously chalte hain, toh link jo true aggregate move kar sakta hai woh double hai.

Overhead (wasted fraction) dono taraf: ${\text{Overhead}}_{8b/10b}=\frac{10-8}{10}=20\%{\text{Overhead}}_{128b/130b}=\frac{130-128}{130}=1.538\%$ Waste-reduction ratio (wasted slice kitni chhoti ho gayi): $\frac{20\%}{1.538\%}\approx 13.0\times$ Usable-efficiency ratio (encoding akele se actually kitna zyada data jaata hai, per lane): $\frac{98.46\%}{80\%}\approx 1.23\times$ Yeh kyun alag hain: wasted part 13× shrink hua, lekin kyunki 80% already usable tha, usable part sirf 80% se 98.46% tak chadh sakta tha — ek modest 1.23× gain. 13× data increase ke liye jagah nahi hai kyunki tum kabhi 100% usable se zyada nahi ja sakte.

Same encoding, toh $L\times R$ compare karo. $\text{x8 Gen 4: }\frac{8\times 16\times 0.98462}{8}=8\times 2\times 0.98462=15.75\text{GB/s}$ $\text{x16 Gen 3: }\frac{16\times 8\times 0.98462}{8}=16\times 1\times 0.98462=15.75\text{GB/s}$ Yeh match karte hain — claim TRUE hai. Yeh kyun kaam karta hai: master formula mein product $L\times R$ matter karta hai (efficiency aur ÷8 dono mein shared hain). Lanes half karna ($16\to 8$) lekin rate double karna ($8\to 16$) $L\times R$ ko unchanged chhodhta hai: dono mein $128$. Yeh general rule hai "har generation tumhe same bandwidth ke liye lane count aadha karne deta hai."

Part 1 — same line, do descriptions. Ek baud ek symbol per second hai. Yahan ek transfer ek bit-equivalent hai. PAM-4 per symbol 2 bits bhejta hai, toh: $32\text{Gbaud}\times 2\frac{\text{bits}}{\text{symbol}}=64\text{Gbit-equivalents/s}=64\text{GT/s}$ "64 GT/s" figure mein already 2-bits/symbol fold in hai; tum dobara 2 se multiply nahi karte.

Part 2 — FLIT efficiency. Ek FLIT block wire par 256 bytes hai lekin sirf 242 useful payload hain: $E=\frac{242}{256}=0.94531$ Move A + Move B (per direction): $BW=\frac{16\times 64\times 0.94531}{8}=\frac{16\times 64\times 0.94531}{8}$ $=16\times 8\times 0.94531=128\times 0.94531=121.0\text{GB/s (per direction)}$ Bidirectional aggregate: $121.0\times 2=242\text{GB/s}$ — spec headline figure se match karta hai (jo bidirectional number quote karta hai).

Kyun decibels, kyun yeh ratio: ek receiver ki levels alag karne ki ability voltage gap ke saath scale hoti hai unke beech mein. Gap ko aadha — ya yahan, tera — karna noise ko teen guna zyada likely banata hai ki symbol galat level mein chala jaaye. Engineers aisi ratios ko logarithmically decibels mein measure karte hain; ek voltage ratio ke liye formula hai $20{\log }_{10}(\cdot )$.

Gap ratio: $\frac{{\text{gap}}_{NRZ}}{{\text{gap}}_{PAM4}}=\frac{2V}{2V/3}=3$ SNR penalty: $20{\log }_{10}(3)=20\times 0.4771=9.54\text{dB}$ FEC kyun mandatory ho jaata hai: ~9.5 dB margin lose karne ka matlab hai bahut zyada raw symbol errors, toh PAM-4 links ab sirf retransmission par reliable rehne ke liye rely nahi kar sakte — forward error correction errors ko in-place repair karta hai costly retries force karne se pehle, latency aur throughput ko sane rakhta hai.

True per-direction ceiling (Move A + Move B, FLIT efficiency $242/256$): $BW=\frac{4\times 64\times 0.94531}{8}=4\times 8\times 0.94531=32\times 0.94531=30.25\text{GB/s}$ Toh ek sequential read (ek direction) 30.25 GB/s ke paas top out karta hai, 60 nahi. Likely mis-count: $30.25\times 2\approx 60.5$ GB/s — vendor ne bidirectional aggregate (TX + RX summed) ko read speed ki tarah quote kiya. Kyun yeh misleading hai: ek read ek direction mein data pull karta hai; reverse path sirf tiny acknowledgements carry karta hai, toh uski bandwidth sequential reads mein help nahi karti. Fix / reviewer's point: headline "×2" numbers aggregate hain, achievable one-way throughput nahi.

x16 Gen 3 per-direction bandwidth ::: 15.75 GB/s Gen 1 x1 per-direction bandwidth ::: 250 MB/s Efficiency of 128b/130b ::: 128/130 ≈ 98.46% Efficiency of FLIT 242/256 ::: ≈ 94.53% Waste-reduction ratio Gen2→Gen3 ::: ≈ 13× (sirf wasted fraction ka) Usable-efficiency ratio Gen2→Gen3 ::: ≈ 1.23× PAM-4 SNR penalty vs NRZ ::: ≈ 9.54 dB x4 Gen 6 per-direction ceiling ::: ≈ 30.25 GB/s