PCI Express (PCIe) architecture and generations: Worked examples

6.3.2 · D3 · Hardware › Interconnects, Buses & SoC › PCI Express (PCIe) architecture and generations

Yeh page PCI Express architecture and generations ke liye calculator ka playground hai. Parent note tumhe formulas deta hai; yahan hum unhe har us situation se drive karte hain jo exam mein aa sakti hai — tiny x1 link, huge x16 link, do alag encodings, sneaky "13× vs 1.23×" trap, aur ek PAM-4 signal-quality problem. End tak, PCIe throughput ke baare mein koi bhi exam question tumhe surprise nahi karega.

Neeche har ek number machine-checked hai. Agar tum koi worked example follow karo aur alag number aaye, toh tumne typo dhundha, vault ne nahi.

Scenario matrix

Ek bhi number touch karne se pehle, chalte hain har tarah ke questions map out karte hain jo yeh topic throw kar sakta hai. Socho isko ek chessboard ki tarah: har square ek "case class" hai, aur hum ensure karenge ki kam se kam ek worked example har square pe land kare.

Cell	Kya alag hai	Kaun sa example cover karta hai
A — tiny link	$L = 1$ lane (sabse chhota, per-lane errors pakadta hai)	Example 1
B — wide link	$L = 16$ lanes (aggregation)	Example 2
C — old encoding	8b/10b, efficiency $= \frac{8}{10}$	Example 1, 3
D — new encoding	128b/130b, efficiency $= \frac{128}{130}$	Example 2, 4
E — the ratio trap	"13× less waste" vs "1.23× more data"	Example 5
F — degenerate / zero	$L = 0$ ya "raw = usable?" edge questions	Example 6
G — full-duplex doubling	bidirectional aggregate ke liye 2 se multiply karo	Example 7
H — real-world word problem	"kya ek SSD is slot ko saturate karega?"	Example 8
I — exam twist / PAM-4 SNR	signal-quality, $lo g$ , dB	Example 9

Compute karne se pehle chalte hain har knob ko ek picture ke saath pin down karte hain.

Figure — PCI Express (PCIe) architecture and generations

Yeh figure kya dikhata hai (Figure 1 — master pipeline). Diagram ko left se right padho jaise ek assembly line jo ek bandwidth number manufacture karti hai. Lane-count box bilkul left mein (lavender, aur rectangle ki tarah drawn) tumhara lane count $L$ hai — link mein kitne independent wire-pairs hain. Arrow feed karta hai raw-rate box mein (coral, rounded rectangle ki tarah drawn), raw transfer rate $R$ (GT/s = gigatransfers per second mein) jo har lane push karta hai. Woh feed karta hai efficiency box mein (mint, ellipse ki tarah drawn), encoding efficiency $E$ — hamesha 1 se neeche ek fraction, kyunki har encoding clock recovery aur error checking ke liye kuch bits sacrifice karta hai. Aakhir mein duplex box (butter, "?" mark ke saath diamond ki tarah drawn kyunki yeh optional hai) ek optional $\times 2$ hai: isko tabhi on karo jab question dono directions add karke maange. Har box ko ek bold letter (L, R, E, ×2?) se bhi label kiya gaya hai taaki tum colour pe rely kiye bina refer kar sako. Right mein white output box (thick double border ke saath drawn) finished product hai — woh bandwidth jo exam pooch raha hai. Line ke neeche italic caption ek extra move yaad dilata hai: 8 se divide karo agar bytes chahiye bits ki jagah. Har ek example neeche bas yahi line hai jisme char labelled boxes mein alag numbers daale gaye hain.

Ek unit fact jis par hum constantly lean karenge:

Worked examples

Example 1 — Cell A + C: sabse chhota possible link (x1, Gen 1)

Forecast: Abhi guess karo — kya yeh 312 MB/s se zyada hoga ya kam (jo hai 2.5 Gb/s ÷ 8, encoding ignore karke)? Kyunki encoding 20% throw away karta hai, kam expect karo.

Step 1 — knobs set karo. $L = 1$ , $R = 2.5$ GT/s, aur yahan 1 transfer = 1 bit hai, toh yeh $2.5$ Gb/s raw line rate hai. Yeh step kyun? Hum bas scenario ko master formula ke slots mein read kar rahe hain. Gen 1 mein ek bit per transfer hai, toh koi PAM-4 subtlety nahi.

Step 2 — encoding efficiency apply karo. $E = \frac{8}{10} = 0.8$ . $usable bits/s = 2.5 Gb/s \times 0.8 = 2.0 Gb/s$ Yeh step kyun? Wire par har 10 bits mein se sirf 8 tumhara data hai. Toh $0.8$ se multiply karo.

Step 3 — bytes mein convert karo. 8 se divide karo: $\frac{2.0 Gb/s}{8} = 0.25 GB/s = 250 MB/s$ Yeh step kyun? Question MB/s (bytes) mein maang raha hai, aur 8 bits mein ek byte hoti hai.

Answer: 250 MB/s.

Recall Verify: units aur sanity

$2.5 Gb/s \times 0.8 = 2.0 Gb/s$ ✓, aur $2.0/8 = 0.25 GB/s = 250 MB/s$ ✓. Yeh parent note ki Gen 1 x1 row se exactly match karta hai. Aur haan — $250 < 312$ , jaise forecast tha, kyunki encoding ne 20% kha liya.

Example 2 — Cell B + D: sabse wide link (x16, Gen 3)

Forecast: Gen 1 x1 tha 0.25 GB/s. Yeh 16 lanes hai, faster rate, better encoding. 15 GB/s ke aas-paas koi number guess karo.

Step 1 — per-lane usable bits. $8 Gb/s \times \frac{128}{130} = 8 \times 0.98462 = 7.877 Gb/s per lane$ Yeh step kyun? Pehle ek lane ki real data rate nikalo; phir lanes simply multiply hote hain (woh independent hain — koi sharing nahi).

Step 2 — 16 lanes aggregate karo. $16 \times 7.877 = 126.05 Gb/s$ Yeh step kyun? Har lane ek private wire pair hai, toh total data = ek lane × lane count. Koi contention nahi, toh plain multiplication valid hai.

Step 3 — bits se bytes. $\frac{126.05}{8} = 15.76 GB/s$ Yeh step kyun? Answer bytes mein maanga gaya.

Answer: ≈ 15.75 GB/s (one direction).

Recall Verify

$8 \times 128/130 = 7.8769 \dots$ Gb/s ✓; $\times 16 = 126.03$ Gb/s ✓; $\div 8 = 15.754$ GB/s ✓ (parent ke Gen 3 x16 entry 15.75 GB/s se rounds karta hai).

Example 3 — Cell C, doubled rate (x1, Gen 2)

Forecast: Same encoding, exactly double rate → Gen 1 ke 250 ka exactly double expect karo, toh 500 MB/s.

Step 1 — usable bits. $5.0 Gb/s \times 0.8 = 4.0 Gb/s$ . Yeh step kyun? Same 8b/10b machine jaise Example 1 mein, bas faster line rate.

Step 2 — bytes mein. $4.0/8 = 0.5 GB/s = 500 MB/s$ . Yeh step kyun? Byte answer maanga gaya.

Answer: 500 MB/s — exactly Gen 1 ka $2 \times$ .

Recall Verify

$5.0 \times 0.8/8 = 0.5$ GB/s = 500 MB/s ✓, aur $500 = 2 \times 250$ ✓.

Example 4 — Cell D, half-width middle case (x8, Gen 4)

Forecast: Gen 4 x16 famously 31.5 GB/s hai (parent table se). Half lanes → ~15.75 GB/s guess karo.

Step 1 — per-lane. $16 \times \frac{128}{130} = 15.754$ Gb/s. Yeh step kyun? Lane rate pehle, hamesha.

Step 2 — 8 lanes aggregate. $8 \times 15.754 = 126.03$ Gb/s. Yeh step kyun? Lane count multiply karta hai. Notice karo yeh Gen 3 x16 ke Example 2 ke barabar hai — double rate, half lanes cancel out hote hain.

Step 3 — bytes. $126.03/8 = 15.75$ GB/s.

Answer: ≈ 15.75 GB/s.

Recall Verify

$16 \times 128/130 \times 8/8 = 15.754$ GB/s ✓ (15.75 tak rounds). Aur Gen 4 x16 iska double = 31.5 GB/s, parent table se match karta hai.

Example 5 — Cell E: "13× vs 1.23×" ratio trap

Forecast: Do ratios chhupe hue hain. Ek wasted fractions compare karta hai, doosra usable fractions. Woh same nahi hain aur interchangeable nahi hain.

Step 1 — har encoding ka wasted fraction. $waste_{8 b /10 b} = \frac{10 - 8}{10} = 0.20 = 20%$ $waste_{128 b /130 b} = \frac{130 - 128}{130} = 0.01538 = 1.538%$ Yeh step kyun? "Waste" overhead bits divided by total bits hai. Isi ko "less waste" refer karta hai.

Step 2 — dono wastes ka ratio. $\frac{20%}{1.538%} = 13.0$ Yeh step kyun? Yahi "13×" claim ka honest source hai — wasted fraction 13-fold shrink hua.

Step 3 — lekin usable throughput wahi hai jo tum feel karte ho. Efficiencies compare karo, wastes nahi: $\frac{E _{128 b /130 b}}{E _{8 b /10 b}} = \frac{128/130}{8/10} = \frac{0.98462}{0.80} = 1.2308$ Yeh step kyun? Kyunki 80% already through ja raha tha, waste ka aakhri chunk khatam karna tumhe sirf 80% se 98.46% tak lift karta hai — $13 \times$ nahi, $1.23 \times$ gain.

Answer: $13 \times$ = wasted bits ka shrinkage; $1.23 \times$ = usable data ki growth (per lane, sirf encoding change).

Yeh figure kya dikhata hai (Figure 2 — do ratios, side by side). Chart left par do coral bars aur right par do mint bars mein split hota hai, aur bina colour ke readable rehne ke liye har waste bar diagonal-hatch pattern se fill hai jabki har usable bar solid fill hai; har bar par text-label bhi hai ("waste" ya "usable") seedha us par. Waste bars (hatched, coral) wasted fraction hain: left wala tall 20% (8b/10b) hai, right wala stubby 1.54% (128b/130b) — aur lavender double-arrow gap ko "13× shorter" label karta hai. Woh shrinkage real aur honest hai. Ab apni aankhein usable bars (solid, mint) par laao, usable-data fraction: left 80% hai, right 98.46%, aur lavender arrow unhe "only 1.23× taller" label karta hai. Picture ka poora point contrast hai: same encoding change hatched waste bar ko dramatically collapse (13×) karta hai lekin solid usable bar ko sirf thoda sa upar nudge (1.23×) karta hai. Tumhara GPU solid bars feel karta hai, hatched wale nahi — toh encoding change se honest per-lane data gain 1.23× hai, kabhi 13× nahi.

Recall Verify

$0.20/ (2/130) = 13.0$ ✓; $(128/130) / (8/10) = 1.2308$ ✓.

Example 6 — Cell F: degenerate inputs (x0, aur "kya raw = usable?")

Is example ke part (b) ko touch karne se pehle, humen ek term define karna hai jise parent note ne sirf passing mein use kiya.

Definition FLIT (flow-control unit) aur uski efficiency

PCIe 6.0 (Gen 6) se shuru hokar, data FLITs (flow-control units) naam ke fixed-size blocks mein group hota hai. Ek FLIT ek 256-byte block hai, lekin saare 256 bytes tumhara payload nahi hote: kuch bytes block ke apne error-correction (FEC) aur CRC bookkeeping par kharch hote hain. PCIe 6.0 specification mein ek 256-byte FLIT 242 bytes usable data carry karta hai (baaki 14 bytes hain 6 bytes FEC + 8 bytes CRC/overhead). Toh FLIT-level efficiency hai $E_{FLIT} = \frac{242}{256} \approx 0.9453 = 94.53%.$ (Note: Gen 6 bhi ek low-level 256b/257b line code use karta hai jo nearly loss-free hai; parent table jo number "94.53%" ke roop mein quote karta hai woh yeh FLIT payload ratio $242/256$ hai, jo actually tumhara throughput shrink karta hai, toh hum wahi use karte hain.)

Forecast: (a) Zero lanes = zero data, formula ko 0 dena chahiye. (b) Koi generation 100% nahi pahunchi — har encoding kuch cost karti hai.

Step 1 — (a) $L = 0$ plug karo. $B W = 0 \times R \times E \times 2 = 0 Gb/s$ Yeh step kyun? Bina lanes ke link kuch nahi carry karta; formula ko zero pe collapse karna chahiye aur karta hai. Yeh sanity floor hai — hamesha confirm karo ki tumhara formula 0 lanes ke liye 0 deta hai.

Step 2 — (a) bytes mein convert karo. 8 se divide karo: $\frac{0 Gb/s}{8} = 0 GB/s$ Yeh step kyun? Hum same final byte-conversion step phir bhi run karte hain jo har example use karta hai, yeh prove karne ke liye ki yeh accidentally bandwidth introduce nahi karta — zero divided by 8 phir bhi zero hai, jo confirm karta hai ki pipeline degenerate input par bhi consistent hai.

Step 3 — (b) har efficiency check karo.

8b/10b: $E = 0.8 < 1$
128b/130b: $E = 0.98462 < 1$
Gen 6 FLIT: $E = \frac{242}{256} = 0.9453 < 1$

Har ek strictly 1 se below hai. Yeh step kyun? "Efficiency = 100%" ke liye zero overhead bits chahiye honge, lekin clock recovery, DC balance, aur error-check bits mandatory hain. Sabse close 128b/130b hai 98.46% par.

Answer: (a) 0 GB/s. (b) Nahi — highest efficiency 98.46% hai (128b/130b); yeh kabhi 100% nahi pahunchi.

Recall Verify

$0 \times 8 \times 0.98462 \times 2/8 = 0$ ✓; aur $max (0.8, 128/130, 242/256) = 128/130 = 0.98462 < 1$ ✓.

Example 7 — Cell G: full-duplex doubling (x16, Gen 5, aggregate)

Forecast: One-direction Gen 5 x16 Gen 4 ke 31.5 ka double hona chahiye → 63 GB/s. Aggregate phir double → 126 GB/s.

Step 1 — one-direction per lane. $32 \times \frac{128}{130} = 31.508$ Gb/s. Yeh step kyun? Lane rate pehle.

Step 2 — 16 lanes, one direction, bytes mein. $\frac{16 \times 31.508}{8} = 63.02 GB/s$ Yeh step kyun? Yahi number parent table list karta hai (per-direction), jo 63 tak rounds karta hai.

Step 3 — full-duplex ke liye $\times 2$ apply karo. $63.02 \times 2 = 126.03 GB/s aggregate$ Yeh step kyun? Kyunki TX aur RX physically separate wire-pairs hain, dono ek saath full speed par run kar sakte hain — koi ek doosre se bandwidth nahi chhurata. Jab koi question aggregate (dono directions sum) maange, hum do equal one-direction numbers add karne ke liye allowed hain, jo 2 se multiply karne jaisa hi hai.

Answer: ≈ 63 GB/s one direction, ≈ 126 GB/s aggregate.

Recall Verify

$32 \times 128/130 \times 16/8 = 63.02$ GB/s ✓ (63 tak rounds); aggregate $= 126.03$ GB/s ✓ (126 tak rounds).

Example 8 — Cell H: real-world word problem (kya SSD slot ko saturate karega?)

Forecast: Gen 3 x4, x16 (15.75 GB/s) ka quarter hai → lagbhag 3.9 GB/s ≈ 3,900 MB/s. Drive chahti hai 7,000. Bottleneck expect karo.

Step 1 — slot ki one-direction usable rate. $4 \times 8 \times \frac{128}{130} = 31.508 Gb/s$ Yeh step kyun? Reads ek direction mein flow karte hain; hum drive ki read spec se compare karte hain, toh one-direction fair comparison hai.

Step 2 — MB/s mein. $\frac{31.508 Gb/s}{8} = 3.9385 GB/s = 3, 938.5 MB/s$ Yeh step kyun? Drive spec MB/s mein hai, toh matching units mein convert karo. Gb/s ko MB/s se kabhi compare mat karo.

Step 3 — compare karo. Drive chahti hai $7, 000$ MB/s; slot deliver karta hai $\approx 3, 938$ MB/s. Kyunki $3, 938 < 7, 000$ , slot bottleneck hai — drive yahan apni rating ke sirf lagbhag 56% par run kar sakti hai. Yeh step kyun? Ek chain apne slowest link ki speed par chalti hai. Yeh final decision jo question maang raha hai — "kya slot bottleneck karta hai?" — sirf tabhi answer ho sakta hai jab hum dono rates same units mein directly compare karein, jo exactly yeh step karta hai. Jo bhi number chhota ho woh ceiling hai.

Answer: Haan — Gen 3 x4 slot drive ko ~3,938 MB/s par cap karta hai. 7,000 MB/s hit karne ke liye Gen 4 x4 chahiye (double rate → ~7,877 MB/s).

Recall Verify

$4 \times 8 \times 128/130/8 = 3.9385$ GB/s = 3938.5 MB/s $< 7000$ ✓; Gen 4 x4 double ho ke $7877$ MB/s $> 7000$ ✓.

Example 9 — Cell I: exam twist — PAM-4 SNR penalty (Gen 6)

Forecast: (a) Char levels = 2 bits ( $lo g_{2} 4$ ). (b) Levels ke beech gaps teen ke factor se shrink ho jaate hain, aur dB voltage ratio ke liye $20 lo g_{10}$ use karta hai, toh roughly $20 lo g_{10} (3) \approx 9.5$ dB expect karo.

Step 1 — (a) bits per symbol. $b = lo g_{2} (4) = 2 bits/symbol$ Yeh step kyun? Har symbol $4$ levels mein se choose karta hai; encode kiye bits ki sankhya $lo g_{2} (number of levels)$ hai. Isi liye PAM-4 symbol clock raise kiye bina data double karta hai.

Yeh figure kya dikhata hai (Figure 3 — NRZ vs PAM-4 voltage levels). Do "eye" pictures same voltage axis par side by side baithte hain. Left (NRZ): sirf do lavender levels solid lines ke roop mein drawn, $+ V$ matlab bit 1 aur $- V$ matlab bit 0, ek moti coral double-arrow ke saath unke beech $2 V$ ka gap mark karta hua — ek receiver inhe noise ke bawajood asaani se alag kar sakta hai. Right (PAM-4): char mint levels dashed lines ke roop mein drawn ( $- 3 V, - V, + V, + 3 V$ ) same outer span mein cramped, har pair do bits carry karta hai ( $00, 01, 10, 11$ ). Har level ko uski voltage aur bit-pair ke saath text-label kiya gaya hai taaki colour padhne ke liye kabhi zaruri na ho. Coral double-arrow ab neighbouring levels ke beech sirf $\frac{2 V}{3}$ ka gap mark karta hai. Yahi poori kahani hai: teen-guna-narrower gaps matlab woh noise jo NRZ ke liye harmless thi ab ek symbol flip kar sakti hai, isi liye Gen 6 ko error correction add karna padta hai.

Step 2 — (b) voltage separation 3 ke factor se shrink hoti hai. NRZ mein do levels $2 V$ apart hain. PAM-4 mein char levels same outer range span karte hain lekin teen equal steps mein baithte hain, toh neighbouring levels sirf $\frac{2 V}{3}$ apart hain — $3$ guna close. Yeh step kyun? Signal-to-noise margin govern hota hai uss baat se ki jo levels tumhe distinguish karni hain woh kitni door hain. Levels jo 3× close hain tumhe noise ke khilaf 3× less voltage headroom dete hain, toh margin exactly us 3 ke factor se worsen hota hai.

Step 3 — factor-of-3 ko decibels mein convert karo. Voltage/amplitude ratio ke liye decibels $20 lo g_{10}$ use karte hain: $penalty = 20 lo g_{10} (3) = 9.542 dB$ Yeh step kyun? dB signal ratios ka standard engineering unit hai, toh exam answer dB mein chahta hai. Multiplier $20$ hai ( $10$ nahi) kyunki signal power amplitude squared ke roop mein scale karta hai, aur $10 lo g_{10} (V^{2}) = 20 lo g_{10} (V)$ — toh 3 ka amplitude ratio $20 lo g_{10} (3)$ dB ban jaata hai.

Answer: (a) 2 bits/symbol; (b) roughly 9.5 dB worse SNR — jo exactly isi liye hai ki Gen 6 forward error correction (FEC) mandatory karta hai.

Recall Verify

$lo g_{2} 4 = 2$ ✓; $20 lo g_{10} 3 = 9.542$ dB ✓ (parent note ke "≈ 9.5 dB" tak rounds).

Recall gauntlet

Recall Gen 1 se Gen 2 mein kaun sa knob badla?

Sirf rate (2.5 → 5.0 GT/s). Encoding 8b/10b rahi, toh throughput exactly double hua.

Recall "13× less waste" — actually kya 13× hai?

Wasted fraction 13× shrink hua ( $20% \to 1.54%$ ). Usable data sirf 1.23× badha ( $80% \to 98.46%$ ).

Recall Gen 3 x16 one-direction bandwidth?

$8 \times \frac{128}{130} \times 16/8 \approx 15.75$ GB/s.

Recall FLIT kya hai aur uski efficiency 94.53% kyun hai?

FLIT Gen 6 ka fixed 256-byte flow-control block hai; un bytes mein se sirf 242 payload hain (baki FEC + CRC hai), toh $242/256 \approx 94.53%$ .

Recall Full-duplex kyun 2 se multiply karne deta hai?

TX aur RX separate physical pairs hain, toh dono ek saath full speed par run karte hain — kuch bhi shared nahi, toh unhe add karna legitimate hai.

Recall PAM-4 ko FEC kyun chahiye jab NRZ ko nahi tha?

Char levels ~3× close baithte hain → ~9.5 dB worse SNR margin → bahut zyada bit errors → FEC unhe clean karne ke liye mandatory ho jaata hai.