Pipeline registers and control signals: Worked examples

This page is the drill-ground for the parent topic. We do not re-teach the theory; we hammer it against every kind of case until no scenario can surprise you. If a term feels unfamiliar, jump back to the parent and to Single-cycle datapath first.

The scenario matrix

Every problem this topic can throw at you is one of the cells below. A "case class" here is a distinct way pipeline registers or control signals behave. We will cover all of them.

#	Case class	What makes it different	Example that hits it
A	Width arithmetic (normal)	Sum the fields a register must carry	Ex 1
B	Degenerate width (a stage that drops fields)	Later registers get narrower	Ex 2
C	Zero-signal instruction	An instruction that sets a control bit to 0	Ex 3
D	Signal-lifetime trace	One bit's journey across all 4 stages	Ex 4
E	Wrong-register bug (destructive case)	What breaks if dest# is not carried	Ex 5
F	Limiting value (deepest signal)	The signal that must survive the most stages	Ex 6
G	Real-world word problem	Timing / throughput reasoning	Ex 7
H	Exam twist (the "5th register" trap)	Symmetry intuition that is wrong	Ex 8
I	Branch data survival	PC+4 must reach a later stage than fetch	Ex 9

Nine cells, nine worked examples — one per row. Let us walk each.

Worked example Ex 1 — Cell A · Width of ID/EX (normal width arithmetic)

Statement: For a classic 32-bit MIPS, compute the bit-width of the ID/EX register. It must carry: two register-read values, the sign-extended immediate, PC+4, the destination register number, plus all three control bundles (EX = 3 bits, MEM = 3 bits, WB = 2 bits).

Forecast: Guess before reading — will ID/EX be wider or narrower than the EX/MEM (107 bits) from the parent? (Hint: it still carries all three control bundles.)

List every field the register must store. Why this step? A register's width is exactly the sum of what later stages need — nothing carried is free, nothing dropped is recoverable.
- Read data 1: $32$
- Read data 2: $32$
- Sign-extended immediate: $32$
- PC+4: $32$
- Destination reg #: $5$
Add the control bundles. Why this step? ID/EX is the first register, so it holds all signals decoded in ID that any later stage needs: EX(3) + MEM(3) + WB(2) $= 8$ .
Sum. Why this step? Total width = data fields + control fields. $W_{I D / E X} = 32 + 32 + 32 + 32 + 5 + (3 + 3 + 2) = 133 + 8 = 141 bits$

Verify: Data part $= 133$ , control part $= 8$ , total $141$ . Sanity: ID/EX carries more control (8 bits) than EX/MEM (5 bits) because EX/MEM has already dropped the EX bundle — so ID/EX being wider in control is exactly right. ✓

Figure — Pipeline registers and control signals

Worked example Ex 2 — Cell B · Degenerate width: MEM/WB (the narrowest)

Statement: Compute the width of MEM/WB. It carries: memory-read data, ALU result, destination reg #, and only the WB control bundle.

Forecast: MEM/WB is the last pipeline register. Will it be the widest or the narrowest of the four? Guess.

List surviving fields. Why this step? By MEM/WB, everything the earlier stages needed has already been consumed — only what WB needs remains.
- Memory data: $32$ (for a load)
- ALU result: $32$ (for arithmetic that skips memory)
- Dest reg #: $5$
Add the only remaining bundle. Why this step? WB uses RegWrite, MemtoReg — that's the WB bundle, $2$ bits. EX and MEM bundles are already gone.
Sum. $W_{M E M / W B} = 32 + 32 + 5 + 2 = 71 bits$

Verify: $71 < 107 < 141$ , so MEM/WB (71) is the narrowest, EX/MEM (107) is middle, ID/EX (141) widest. The pipeline registers shrink as we go — exactly the "each register drops the bundle just consumed" rule. ✓

Worked example Ex 3 — Cell C · Zero-signal instruction (

sw) Statement: For sw $t0, 4($s1) (store word), what are RegWrite and MemtoReg? Does the WB bundle still travel the whole pipe?

Forecast: A store writes to memory, not to a register. Does that mean the WB bundle can be skipped for this instruction?

Decode the intent. Why this step? sw computes an address (EX) and writes data to memory (MEM). It never writes the register file.
Set the WB signals. Why this step? RegWrite = 0 (no register write). MemtoReg is a don't-care (call it $0$ ) because its output is never used when RegWrite=0.
Does the bundle still ride? Why this step? Yes — the pipeline register is fixed-width hardware. It cannot "skip" a field for one instruction. The WB bundle still travels ID/EX → EX/MEM → MEM/WB carrying RegWrite=0.

Verify: RegWrite=0 arrives at WB and disables the register-file write-enable. So sw correctly writes memory but not registers. The bundle physically travels; its value just happens to be $0$ . Control-bit count still $= 2$ for WB. ✓

Worked example Ex 4 — Cell D · Full lifetime trace of

MemRead for lw Statement: Trace MemRead for lw $s2, 8($s3) cycle by cycle. In which register(s) does it live, and in which stage is it consumed?

Forecast: MemRead is in the MEM bundle. Which pipeline registers must carry it — all of them, or only some?

Cycle 2 (ID): Control unit reads opcode 100011 → MemRead = 1. Why this step? Opcode is visible only in ID.
End of ID → latch into ID/EX: MemRead=1 stored. Why this step? MEM stage is 2 cycles away; must be preserved (part of MEM bundle, which ID/EX holds).
Cycle 3 (EX) → EX/MEM: EX does not use MemRead, so it is copied unchanged. Why this step? A stage passes along paperwork it does not consume; EX/MEM holds MEM+WB bundles.
Cycle 4 (MEM): MemRead=1 drives the data-memory read-enable. Consumed here. Why this step? This is the stage the signal was made for.
After MEM: MemRead is NOT latched into MEM/WB. Why this step? Its stage consumed it; MEM/WB holds only the WB bundle.

Verify: MemRead lives in exactly 2 pipeline registers (ID/EX, EX/MEM) and is consumed in stage 4 (MEM). Consistent with parent's rule "each register drops the bundle just consumed." ✓

Worked example Ex 5 — Cell E · The wrong-register bug (destructive case)

Statement: A student wires the WB stage's write-address to the current IF/ID instruction's rd field instead of the pipelined dest# from MEM/WB. Program:

I1: add $t0, $t1, $t2   ; wants to write $t0 (reg 8)
I2: sub $t3, $t4, $t5   ; wants to write $t3 (reg 11)

When I1 reaches WB, which register actually gets written under the bug?

Forecast: Guess the corrupted target register number before computing.

Line up the pipeline. Why this step? When I1 is in WB (cycle 5), I2 is 1 instruction behind. With single-issue, at cycle 5 the newest instruction in IF is I5, but IF/ID holds the instruction fetched in cycle 4, i.e. I4 (if the pipe is full). The rd field visible in IF/ID is I4's, not I1's.
Identify the correct vs buggy address. Why this step? Correct: MEM/WB carries dest# $= 8$ ( $t 0$ ). Buggy: reads whatever rd sits in IF/ID that cycle — a different, younger instruction's target.
State the corruption. Why this step? I1's result ($t1+$t2) gets written into the wrong register (the one named in IF/ID), and $t0 is never updated. Every subsequent read of $t0 is stale.

Verify: The fix is exactly the parent's rule: latch the 5-bit dest# through ID/EX → EX/MEM → MEM/WB so WB uses the older instruction's field. Correct target for I1 $= 8$ ; the bug writes some other number → data corruption. ✓ (This is the classic datapath error.)

Worked example Ex 6 — Cell F · Limiting value: the longest-living signal

Statement: Which control signal must survive the most pipeline registers, and how many? Prove no signal outlives it.

Forecast: Guess: is it an EX signal, a MEM signal, or a WB signal?

Count survival distance per bundle. Why this step? A signal's "lifetime" = number of pipeline registers it passes through before consumption.
- EX bundle: consumed in EX → rides only ID/EX = 1 register.
- MEM bundle: consumed in MEM → rides ID/EX, EX/MEM = 2 registers.
- WB bundle: consumed in WB → rides ID/EX, EX/MEM, MEM/WB = 3 registers.
Take the maximum. Why this step? The signal that lives longest is the one whose consuming stage is farthest from ID. WB is the farthest stage.
Answer: WB signals (RegWrite, MemtoReg) survive 3 pipeline registers — the limiting (maximum) case.

Verify: $max (1, 2, 3) = 3$ , achieved by the WB bundle. No stage is later than WB, so no signal can exceed 3 register-hops. ✓

Worked example Ex 7 — Cell G · Real-world word problem (throughput vs registers)

Statement: A pipeline register adds a setup+propagation delay of 0.1 ns to each stage boundary. Each of the 5 combinational stages needs 2.0 ns of work. What is the clock period, and how does adding the (4) pipeline registers change the per-instruction latency vs a single-cycle CPU that does all 5 stages in one 10.0 ns clock?

Forecast: Does pipelining make a single instruction finish faster or slower? Guess.

Clock period of the pipeline. Why this step? The clock must be long enough for the slowest stage plus its register overhead. $T_{c l k} = 2.0 + 0.1 = 2.1 ns$
Latency of one instruction through the pipe. Why this step? It must pass all 5 stages, each taking one clock. $L_{p i p e} = 5 \times 2.1 = 10.5 ns$
Compare to single-cycle. Why this step? Single-cycle finishes one instruction in $10.0$ ns. So a lone instruction is slightly slower ( $10.5 > 10.0$ ) because of the 4 register overheads.
Throughput payoff. Why this step? Once the pipe is full, one instruction completes every $2.1$ ns, vs one every $10.0$ ns single-cycle — a $10.0/2.1 \approx 4.76 \times$ speedup for large programs.

Verify: $T_{c l k} = 2.1$ ns; single-instruction latency $10.5$ ns $> 10.0$ ns (registers cost you on latency); steady-state throughput ratio $10.0/2.1 = 4.7619...$ ✓ The registers buy throughput at the price of a little latency — see Clocking and edge-triggered flip-flops.

Worked example Ex 8 — Cell H · Exam twist: "how many registers, and why not 5?"

Statement: A 5-stage pipeline has walls between stages. A student writes "5 stages ⇒ 5 pipeline registers." How many are there really, and prove the count.

Forecast: Guess the number and the location of the "missing" wall.

Count the boundaries between stages. Why this step? A pipeline register sits between two stages, not inside one. With 5 stages in a row, the internal boundaries are IF|ID, ID|EX, EX|MEM, MEM|WB — that's 4 gaps.
Check the ends. Why this step? Before IF there is the PC (already a register); after WB the output goes into the register file, which is already stateful storage.
Conclude. Why this step? Adding a wall after WB would just delay the write by one cycle and worsen hazards (see Pipeline hazards). So the count is 4, not 5.

Verify: $5 stages - 1 = 4$ internal boundaries $= 4$ registers (IF/ID, ID/EX, EX/MEM, MEM/WB). The intuition "5 stages ⇒ 5 registers" is off by exactly one. ✓

Worked example Ex 9 — Cell I · Branch data survival: PC+4 reaching EX

Statement: For beq $t0, $t1, LABEL with the branch offset encoded as imm = 6, PC+4 $= 0 x 00400020$ . The branch target is computed in EX. Which pipeline registers must carry PC+4, and what is the target address?

Forecast: PC+4 is produced in fetch (IF). Guess which registers must relay it to EX.

Locate where PC+4 is used. Why this step? Branch target $= PC+4 + (imm ≪ 2)$ is computed in EX, so PC+4 must survive fetch → decode → execute.
Trace the carrying registers. Why this step? PC+4 must be latched into IF/ID (fetch→decode) and ID/EX (decode→execute) to reach the EX adder.
Compute the target. Why this step? Shift the immediate left by 2 (word-align: $6 ≪ 2 = 24 = 0 x 18$ ) and add to PC+4. $target = 0 x 00400020 + 0 x 18 = 0 x 00400038$

Verify: $imm ≪ 2 = 6 \times 4 = 24 = 0 x 18$ . $0 x 00400020 = 4194336$ , $+ 24 = 4194360 = 0 x 00400038$ . PC+4 rides IF/ID and ID/EX (2 registers). This matches the parent's mistake-fix: "PC+4 must survive to EX." ✓

Recall Quick self-test on the matrix

Widest pipeline register and its width? ::: ID/EX at 141 bits (holds all 3 control bundles). Narrowest pipeline register and its width? ::: MEM/WB at 71 bits (only WB bundle). How many registers does a WB signal traverse? ::: 3 (ID/EX, EX/MEM, MEM/WB). Does a store instruction still carry a WB bundle? ::: Yes — fixed-width hardware; it carries RegWrite=0. Clock period if each stage is 2.0 ns and register overhead is 0.1 ns? ::: 2.1 ns.

Connections

Pipeline registers and control signals — the parent this page drills
Single-cycle datapath — the 10 ns baseline in Ex 7
Pipeline hazards — why an extra WB register (Ex 8) worsens things
Forwarding and stalling — how the staggered dest# from Ex 5 gets used
Clocking and edge-triggered flip-flops — the register overhead in Ex 7