Pipeline registers and control signals: Worked examples

5.2.4 · D3 · Hardware › Processor Datapath & Pipelining › Pipeline registers and control signals

Ye page parent topic ke liye drill-ground hai. Hum yahan theory dobara nahi padhate; hum isko har tarah ke case ke against itna marte hain jab tak koi bhi scenario surprise na kar sake. Agar koi term unfamiliar lage, pehle parent pe aur Single-cycle datapath pe jaao.

The scenario matrix

Is topic ka har problem neeche diye gaye cells mein se kisi ek mein fit hota hai. Yahan "case class" ka matlab hai ek alag tarika jisme pipeline registers ya control signals behave karte hain. Hum inhe sab cover karenge.

#	Case class	Kya alag hai isme	Example jo isse hit karta hai
A	Width arithmetic (normal)	Ek register ke fields ka sum karo	Ex 1
B	Degenerate width (ek stage jo fields drop karta hai)	Baad ke registers narrower hote hain	Ex 2
C	Zero-signal instruction	Ek instruction jo ek control bit ko 0 set karta hai	Ex 3
D	Signal-lifetime trace	Ek bit ka safar sab 4 stages mein	Ex 4
E	Wrong-register bug (destructive case)	Kya toot ta hai agar dest# carry nahi hota	Ex 5
F	Limiting value (deepest signal)	Woh signal jo sabse zyada stages survive karta hai	Ex 6
G	Real-world word problem	Timing / throughput reasoning	Ex 7
H	Exam twist (the "5th register" trap)	Symmetry intuition jo galat hai	Ex 8
I	Branch data survival	PC+4 ko fetch se baad ke stage tak pahunchna padta hai	Ex 9

Nau cells, nau worked examples — ek per row. Chalte hain ek-ek kar ke.

Worked example Ex 1 — Cell A · Width of ID/EX (normal width arithmetic)

Statement: Classic 32-bit MIPS ke liye, ID/EX register ki bit-width compute karo. Isse carry karna hai: do register-read values, sign-extended immediate, PC+4, destination register number, plus teeno control bundles (EX = 3 bits, MEM = 3 bits, WB = 2 bits).

Forecast: Padhne se pehle guess karo — kya ID/EX, parent ke EX/MEM (107 bits) se wider hoga ya narrower? (Hint: isme abhi bhi teeno control bundles hain.)

Har woh field list karo jo register ko store karni hai. Yeh step kyun? Ek register ki width exactly usi ka sum hai jo baad ke stages ko chahiye — jo carry hota hai woh free nahi hai, jo drop ho gaya woh recover nahi ho sakta.
- Read data 1: $32$
- Read data 2: $32$
- Sign-extended immediate: $32$
- PC+4: $32$
- Destination reg #: $5$
Control bundles add karo. Yeh step kyun? ID/EX pehla register hai, isliye yeh sab signals hold karta hai jo ID mein decode hue aur kisi bhi baad ke stage ko chahiye: EX(3) + MEM(3) + WB(2) $= 8$ .
Sum karo. Yeh step kyun? Total width = data fields + control fields. $W_{I D / E X} = 32 + 32 + 32 + 32 + 5 + (3 + 3 + 2) = 133 + 8 = 141 bits$

Verify: Data part $= 133$ , control part $= 8$ , total $141$ . Sanity check: ID/EX zyada control carry karta hai (8 bits) EX/MEM (5 bits) se, kyunki EX/MEM EX bundle pehle hi drop kar chuka hai — toh ID/EX ka control mein wider hona bilkul sahi hai. ✓

Figure — Pipeline registers and control signals

Worked example Ex 2 — Cell B · Degenerate width: MEM/WB (the narrowest)

Statement: MEM/WB ki width compute karo. Yeh carry karta hai: memory-read data, ALU result, destination reg #, aur sirf WB control bundle.

Forecast: MEM/WB aakhri pipeline register hai. Kya yeh charon mein sabse widest hoga ya narrowest? Guess karo.

Surviving fields list karo. Yeh step kyun? MEM/WB tak pahunchte-pahunchte, jo kuch bhi earlier stages ko chahiye tha woh sab consume ho chuka hai — sirf wahi bacha hai jo WB ko chahiye.
- Memory data: $32$ (load ke liye)
- ALU result: $32$ (arithmetic ke liye jo memory skip karta hai)
- Dest reg #: $5$
Sirf bacha hua bundle add karo. Yeh step kyun? WB use karta hai RegWrite, MemtoReg — yahi WB bundle hai, $2$ bits. EX aur MEM bundles pehle hi ja chuke hain.
Sum karo. $W_{M E M / W B} = 32 + 32 + 5 + 2 = 71 bits$

Verify: $71 < 107 < 141$ , toh MEM/WB (71) narrowest hai, EX/MEM (107) middle mein, ID/EX (141) widest. Pipeline registers shrink hote hain jaise-jaise hum aage badhte hain — exactly "har register us bundle ko drop karta hai jo abhi consume hua" rule. ✓

Worked example Ex 3 — Cell C · Zero-signal instruction (

sw) Statement: sw $t0, 4($s1) (store word) ke liye, RegWrite aur MemtoReg kya hain? Kya WB bundle phir bhi poori pipe mein travel karta hai?

Forecast: Ek store memory mein likhta hai, register mein nahi. Kya iska matlab hai ki WB bundle is instruction ke liye skip kiya ja sakta hai?

Intent decode karo. Yeh step kyun? sw ek address compute karta hai (EX) aur data ko memory mein write karta hai (MEM). Yeh kabhi register file mein nahi likhta.
WB signals set karo. Yeh step kyun? RegWrite = 0 (koi register write nahi). MemtoReg ek don't-care hai (isko $0$ keh lo) kyunki jab RegWrite=0 ho toh iska output kabhi use nahi hota.
Kya bundle phir bhi ride karta hai? Yeh step kyun? Haan — pipeline register fixed-width hardware hai. Yeh kisi ek instruction ke liye koi field "skip" nahi kar sakta. WB bundle phir bhi ID/EX → EX/MEM → MEM/WB mein travel karta hai RegWrite=0 le kar.

Verify: RegWrite=0 WB stage pe pahunchta hai aur register-file write-enable ko disable kar deta hai. Toh sw sahi se memory mein likhta hai lekin registers mein nahi. Bundle physically travel karta hai; iska value bas $0$ hota hai. Control-bit count WB ke liye abhi bhi $= 2$ hai. ✓

Worked example Ex 4 — Cell D ·

lw ke liye MemRead ka full lifetime trace Statement: lw $s2, 8($s3) ke liye MemRead ko cycle by cycle trace karo. Kis register(s) mein yeh rehta hai, aur kis stage mein consume hota hai?

Forecast: MemRead MEM bundle mein hai. Kaun se pipeline registers isse carry karte hain — sab, ya kuch hi?

Cycle 2 (ID): Control unit opcode 100011 padhta hai → MemRead = 1. Yeh step kyun? Opcode sirf ID mein visible hota hai.
ID ke end mein → ID/EX mein latch: MemRead=1 store hota hai. Yeh step kyun? MEM stage 2 cycles door hai; preserve karna padega (MEM bundle ka part, jo ID/EX hold karta hai).
Cycle 3 (EX) → EX/MEM: EX MemRead use nahi karta, toh yeh unchanged copy hota hai. Yeh step kyun? Ek stage woh paperwork aage bhejta hai jo woh consume nahi karta; EX/MEM MEM+WB bundles hold karta hai.
Cycle 4 (MEM): MemRead=1 data-memory read-enable drive karta hai. Yahan consume hota hai. Yeh step kyun? Yahi woh stage hai jiske liye signal banaya gaya tha.
MEM ke baad: MemRead MEM/WB mein latch nahi hota. Yeh step kyun? Iske stage ne isse consume kar liya; MEM/WB sirf WB bundle hold karta hai.

Verify: MemRead exactly 2 pipeline registers (ID/EX, EX/MEM) mein rehta hai aur stage 4 (MEM) mein consume hota hai. Parent ke rule se consistent: "har register us bundle ko drop karta hai jo abhi consume hua." ✓

Worked example Ex 5 — Cell E · Wrong-register bug (destructive case)

Statement: Ek student WB stage ke write-address ko current IF/ID instruction ke rd field se wire karta hai, MEM/WB ke pipelined dest# se nahi. Program:

I1: add $t0, $t1, $t2   ; wants to write $t0 (reg 8)
I2: sub $t3, $t4, $t5   ; wants to write $t3 (reg 11)

Jab I1 WB pe pahunchta hai, bug ki wajah se actually kaunsa register write hota hai?

Forecast: Compute karne se pehle corrupt target register number guess karo.

Pipeline line up karo. Yeh step kyun? Jab I1 WB mein hai (cycle 5), I2 1 instruction peeche hai. Single-issue ke saath, cycle 5 mein IF mein naya instruction I5 hoga, lekin IF/ID us instruction ko hold karta hai jo cycle 4 mein fetch hua, yaani I4 (agar pipe full hai). IF/ID mein jo rd field visible hai woh I4 ka hai, I1 ka nahi.
Correct vs buggy address identify karo. Yeh step kyun? Correct: MEM/WB dest# $= 8$ ( $t 0$ ) carry karta hai. Buggy: jo bhi rd us cycle IF/ID mein baitha hai use read karta hai — ek alag, younger instruction ka target.
Corruption state karo. Yeh step kyun? I1 ka result ($t1+$t2) galat register mein write ho jaata hai (jo IF/ID mein naam hai), aur $t0 kabhi update nahi hota. $t0 ka har baad ka read stale hota hai.

Verify: Fix exactly parent ka rule hai: 5-bit dest# ko ID/EX → EX/MEM → MEM/WB mein latch karo taaki WB puraane instruction ka field use kare. I1 ke liye correct target $= 8$ ; bug kuch aur number likhta hai → data corruption. ✓ (Yeh woh classic datapath error hai.)

Worked example Ex 6 — Cell F · Limiting value: sabse zyada jeene wala signal

Statement: Kaunsa control signal sabse zyada pipeline registers survive karta hai, aur kitne? Prove karo ki koi signal isse zyada nahi jeeta.

Forecast: Guess karo: kya yeh EX signal hai, MEM signal hai, ya WB signal hai?

Har bundle ke liye survival distance count karo. Yeh step kyun? Ek signal ki "lifetime" = wo pipeline registers ki sankhya jinse woh consumption se pehle guzarta hai.
- EX bundle: EX mein consume hota hai → sirf ID/EX mein ride karta hai = 1 register.
- MEM bundle: MEM mein consume hota hai → ID/EX, EX/MEM mein ride karta hai = 2 registers.
- WB bundle: WB mein consume hota hai → ID/EX, EX/MEM, MEM/WB mein ride karta hai = 3 registers.
Maximum lo. Yeh step kyun? Sabse zyada jeene wala signal woh hai jiska consuming stage ID se sabse door hai. WB sabse door stage hai.
Answer: WB signals (RegWrite, MemtoReg) 3 pipeline registers survive karte hain — limiting (maximum) case.

Verify: $max (1, 2, 3) = 3$ , WB bundle se achieve hota hai. WB se koi stage baad mein nahi hai, toh koi signal 3 register-hops se zyada nahi kar sakta. ✓

Worked example Ex 7 — Cell G · Real-world word problem (throughput vs registers)

Statement: Ek pipeline register har stage boundary pe setup+propagation delay of 0.1 ns add karta hai. Pachon combinational stages ko 2.0 ns kaam chahiye. Clock period kya hai, aur (4) pipeline registers add karne se per-instruction latency kaise change hoti hai ek single-cycle CPU se compare karke jo sab 5 stages ek 10.0 ns clock mein karta hai?

Forecast: Kya pipelining ek instruction ko faster finish karati hai ya slower? Guess karo.

Pipeline ka clock period. Yeh step kyun? Clock itna lamba hona chahiye ki sabse slow stage plus uske register overhead ke liye kaafi ho. $T_{c l k} = 2.0 + 0.1 = 2.1 ns$
Pipe mein se ek instruction ki latency. Yeh step kyun? Use sab 5 stages pass karne hain, har ek ek clock leta hai. $L_{p i p e} = 5 \times 2.1 = 10.5 ns$
Single-cycle se compare karo. Yeh step kyun? Single-cycle ek instruction $10.0$ ns mein finish karta hai. Toh ek akela instruction thoda slower hai ( $10.5 > 10.0$ ) kyunki 4 register overheads hain.
Throughput payoff. Yeh step kyun? Jab pipe full ho, har $2.1$ ns mein ek instruction complete hoti hai, vs single-cycle mein har $10.0$ ns mein — bade programs ke liye $10.0/2.1 \approx 4.76 \times$ speedup.

Verify: $T_{c l k} = 2.1$ ns; single-instruction latency $10.5$ ns $> 10.0$ ns (registers latency pe cost karte hain); steady-state throughput ratio $10.0/2.1 = 4.7619...$ ✓ Registers thodi latency ki keemat par throughput khareedते hain — dekho Clocking and edge-triggered flip-flops.

Worked example Ex 8 — Cell H · Exam twist: "kitne registers hain, aur 5 kyun nahi?"

Statement: Ek 5-stage pipeline mein stages ke beech walls hain. Ek student likhta hai "5 stages ⇒ 5 pipeline registers." Actual mein kitne hain, aur count prove karo.

Forecast: Number aur "missing" wall ki location guess karo.

Stages ke beech boundaries count karo. Yeh step kyun? Ek pipeline register do stages ke beech hota hai, kisi ek ke andar nahi. 5 stages row mein hone par, internal boundaries hain IF|ID, ID|EX, EX|MEM, MEM|WB — yeh 4 gaps hain.
Ends check karo. Yeh step kyun? IF se pehle PC hai (pehle se ek register); WB ke baad output register file mein jaata hai, jo pehle se hi stateful storage hai.
Conclude karo. Yeh step kyun? WB ke baad ek wall add karna sirf write ko ek cycle delay karega aur hazards worse banayega (dekho Pipeline hazards). Toh count hai 4, 5 nahi.

Verify: $5 stages - 1 = 4$ internal boundaries $= 4$ registers (IF/ID, ID/EX, EX/MEM, MEM/WB). "5 stages ⇒ 5 registers" intuition exactly ek se galat hai. ✓

Worked example Ex 9 — Cell I · Branch data survival: PC+4 ka EX tak pahunchna

Statement: beq $t0, $t1, LABEL ke liye jisme branch offset imm = 6 encode hai, PC+4 $= 0 x 00400020$ . Branch target EX mein compute hota hai. Kaun se pipeline registers PC+4 carry karte hain, aur target address kya hai?

Forecast: PC+4 fetch (IF) mein produce hota hai. Guess karo kaun se registers isse EX tak relay karte hain.

Pata karo PC+4 kahan use hota hai. Yeh step kyun? Branch target $= PC+4 + (imm ≪ 2)$ EX mein compute hota hai, toh PC+4 ko fetch → decode → execute survive karna padega.
Carrying registers trace karo. Yeh step kyun? PC+4 ko IF/ID (fetch→decode) aur ID/EX (decode→execute) mein latch hona chahiye taaki EX adder tak pahunche.
Target compute karo. Yeh step kyun? Immediate ko left 2 se shift karo (word-align: $6 ≪ 2 = 24 = 0 x 18$ ) aur PC+4 mein add karo. $target = 0 x 00400020 + 0 x 18 = 0 x 00400038$

Verify: $imm ≪ 2 = 6 \times 4 = 24 = 0 x 18$ . $0 x 00400020 = 4194336$ , $+ 24 = 4194360 = 0 x 00400038$ . PC+4 IF/ID aur ID/EX mein ride karta hai (2 registers). Yeh parent ke mistake-fix se match karta hai: "PC+4 ko EX tak survive karna chahiye." ✓

Recall Matrix par quick self-test

Sabse widest pipeline register aur uski width? ::: ID/EX, 141 bits par (teeno control bundles hold karta hai). Sabse narrowest pipeline register aur uski width? ::: MEM/WB, 71 bits par (sirf WB bundle). Ek WB signal kitne registers traverse karta hai? ::: 3 (ID/EX, EX/MEM, MEM/WB). Kya ek store instruction phir bhi WB bundle carry karta hai? ::: Haan — fixed-width hardware; yeh RegWrite=0 carry karta hai. Clock period agar har stage 2.0 ns hai aur register overhead 0.1 ns hai? ::: 2.1 ns.

Connections

Pipeline registers and control signals — woh parent jise yeh page drill karta hai
Single-cycle datapath — Ex 7 mein 10 ns baseline
Pipeline hazards — kyun ek extra WB register (Ex 8) cheezein worse banata hai
Forwarding and stalling — Ex 5 ka staggered dest# kaise use hota hai
Clocking and edge-triggered flip-flops — Ex 7 mein register overhead