Pipeline registers and control signals: Foundations

Before you can understand pipeline registers, you must own every word the parent note leaned on. Below, each symbol is built from absolute zero: plain meaning → the picture → why the topic needs it. Read top to bottom; each one is the ground the next stands on.

1. A "signal" — a wire that is either high or low

Look at the top of the first figure: a single wire drawn as a straight line, labelled with its value $0$ or $1$ . Why we need it: the parent note talks about RegWrite, MemRead, and so on — each of those is one such wire. If you don't picture a wire holding a single bit, "control signal" is just a word.

2. A "bit" and a "bus" — one wire vs. a ribbon of wires

In the second row of the figure, one thin line is a bit; a fat ribbon of 32 lines is a 32-bit bus. Why we need it: the parent writes "ALU result = 32 bits", "dest reg # = 5 bits". Each number is a bus of that width. When we later sum widths to size a register, we are literally counting wires.

3. Combinational logic — a function with no memory

Picture a machine with input wires on the left and output wires on the right, and inside just a tangle of gates — no clock, no storage. The ALU, the adders, the multiplexers of the Single-cycle datapath are all this kind of block.

4. The clock — the drumbeat that marches everything forward

In the figure, the clock is drawn as a square wave — flat low, jump up, flat high, jump down — with the rising edges marked by amber arrows. Every stage of the pipeline does exactly one cycle of work between two rising edges.

Why we need it: "latch on the clock edge" is the sentence the whole topic rests on. Without knowing what an edge is, "edge-triggered register" is empty.

Recall Why a steady drumbeat and not "whenever ready"?

Because 5 stages must hand off in lockstep — a tray only moves when everyone has finished their slice of the cycle. A shared clock guarantees they all step together. See Clocking and edge-triggered flip-flops.

5. A register — the wall with memory (edge-triggered flip-flop)

The right side of Figure 2 shows one register as a box: an input bus $D$ on the left, an output bus $Q$ on the right, and a little triangle on the clock line meaning "edge-triggered". At each amber edge, whatever is on $D$ gets snapshotted onto $Q$ and held.

6. The five stages — the five workers

Figure 3 draws these as five boxes left-to-right, with a register wall between each pair. Count the walls: between IF–ID, ID–EX, EX–MEM, MEM–WB — that is four walls, giving the four registers named IF/ID, ID/EX, EX/MEM, MEM/WB. After WB there is no wall, because WB writes into the register file which is already memory.

Why we need it: every register is named by the two stages it sits between. If the stages are fuzzy, the names IF/ID and EX/MEM are just noise.

7. The opcode — the instruction's ID badge

Picture the 32-bit instruction bus split into labelled fields — opcode, register numbers, immediate. Why we need it: the opcode is only visible in ID. That single fact forces every control signal to be born in ID, which is the heart of why signals must then travel.

8. The register file and the register number (5 bits)

Why we need it: the parent stresses that the destination register number (5 bits) must ride ID/EX → EX/MEM → MEM/WB, or WB writes to the wrong register. That "5" is the answer to $2^{5} = 32$ .

9. Control signals — the sticky notes

The parent groups them into three bundles by which stage uses them:

Bundle	Signals	Used in	Width
EX	ALUSrc, ALUOp, RegDst	EX	$\approx 3$
MEM	MemRead, MemWrite, Branch	MEM	$3$
WB	RegWrite, MemtoReg	WB	$2$

Why we need it: control signals are born in ID but consumed later, so they must be stored inside pipeline registers and carried forward, dropping off each bundle at its stage. That is the parent's central mechanism — see Control unit design.

0

(low) and

1

(high).

How many wires does a 32-bit bus have?

32 parallel wires, carrying one 32-bit number.

What does

∣ M E M ∣ = 3

mean?

The MEM control bundle is 3 wires (bits) wide.

Why can't combinational logic hold a value between cycles?

It has no memory — its output depends only on the inputs present right now.

What exactly happens to a register at the rising clock edge?

It copies its input

D

to its output

Q

and then holds it frozen until the next edge.

Name the five stages in order.

IF, ID, EX, MEM, WB.

Why are there four pipeline registers, not five?

There are only four walls between the five stages; after WB the register file already provides storage.

In which stage is the opcode visible, and why does that matter?

In ID only — so all control signals must be generated there and then transported forward.

Why is a register number exactly 5 bits?

Because

2^{5} = 32

and there are 32 registers to address.

How do you compute a pipeline register's width?

Add the wire-count of every field a later stage still needs — nothing more, nothing less.

Connections

Pipeline registers and control signals (Hinglish) — the parent topic these foundations unlock
Single-cycle datapath — where combinational logic and the five stages first appear as one long path
Clocking and edge-triggered flip-flops — the deep story of the clock edge and the register
Control unit design — how the opcode becomes the control signals
Pipeline hazards — what goes wrong once results and signals are staggered across these registers
Forwarding and stalling — the fixes that read straight from these pipeline registers

Foundations — Pipeline registers and control signals