Foundations — Pipeline registers and control signals
5.2.4 · D1· Hardware › Processor Datapath & Pipelining › Pipeline registers aur control signals
Pipeline registers samajhne se pehle, tumhe parent note ke har word ka matlab pata hona chahiye. Neeche, har symbol bilkul zero se banaaya gaya hai: seedha matlab → picture → kyun topic ko yeh chahiye. Upar se neeche padho; har ek woh zameen hai jis par agla khada hai.
1. Ek "signal" — ek wire jo ya toh high hai ya low
Pehle figure ke top par dekho: ek single wire seedhi line ki tarah draw ki gayi hai, jis par uski value ya likhi hai. Kyun yeh chahiye: parent note RegWrite, MemRead, wagerah ki baat karta hai — unme se har ek aisi ek wire hai. Agar tum ek bit hold karne wali wire picture nahi kar sakte, toh "control signal" sirf ek lafz hai.
2. Ek "bit" aur ek "bus" — ek wire vs. wires ki ek ribbon
Figure ki doosri row mein, ek patli line ek bit hai; 32 lines ki ek moti ribbon ek 32-bit bus hai. Kyun yeh chahiye: parent likhta hai "ALU result = 32 bits", "dest reg # = 5 bits". Har number us width ki ek bus hai. Jab hum baad mein ek register ki size ke liye widths add karte hain, toh hum literally wires ginn rahe hote hain.
3. Combinational logic — bina memory ka ek function
Ek machine picture karo jis mein left pe input wires hain aur right pe output wires, aur andar bas gates ka ek tangle — koi clock nahi, koi storage nahi. Single-cycle datapath ka ALU, adders, multiplexers — sab is tarah ke blocks hain.
4. Clock — woh drumbeat jo sab kuch aage badhata hai
Figure mein, clock ko ek square wave ki tarah draw kiya gaya hai — flat low, jump up, flat high, jump down — rising edges amber arrows se mark kiye gaye hain. Pipeline ka har stage rising edges ke beech exactly ek cycle kaam karta hai.
Kyun yeh chahiye: "clock edge par latch karo" woh sentence hai jis par yeh poora topic tika hai. Bina yeh jaane ki edge kya hoti hai, "edge-triggered register" khokha hai.
Recall Kyun ek steady drumbeat aur "jab ready ho" nahi?
Kyunki 5 stages ko lockstep mein hand off karna hota hai — ek tray sirf tab move hoti hai jab sab ne apna cycle ka slice finish kar liya ho. Ek shared clock guarantee karta hai ki sab ek saath step karte hain. Dekho Clocking and edge-triggered flip-flops.
5. Ek register — memory wali deewar (edge-triggered flip-flop)
Figure 2 ka right side ek register ko ek box ki tarah dikhata hai: left par ek input bus , right par ek output bus , aur clock line par ek chota triangle jiska matlab hai "edge-triggered". Har amber edge par, par jo bhi hai woh par snapshot ho jaata hai aur hold ho jaata hai.
6. Paanch stages — paanch workers
Figure 3 inhe paanch boxes left-to-right ke roop mein draw karta hai, har pair ke beech ek register wall ke saath. Walls gino: IF–ID, ID–EX, EX–MEM, MEM–WB ke beech — yeh chaar walls hain, jo IF/ID, ID/EX, EX/MEM, MEM/WB naamon wale chaar registers dete hain. WB ke baad koi wall nahi, kyunki WB register file mein likhta hai jo already memory hai.
Kyun yeh chahiye: har register uss ke naam se jaana jaata hai jis do stages ke beech woh baitha hai. Agar stages fuzzy hain, toh IF/ID aur EX/MEM ke naam sirf shor hain.
7. Opcode — instruction ka ID badge
32-bit instruction bus ko labelled fields mein split karo — opcode, register numbers, immediate. Kyun yeh chahiye: opcode sirf ID mein visible hota hai. Yeh akela fact force karta hai ki har control signal ID mein paida ho, jo ki yahi core reason hai ki signals ko phir travel karna padta hai.
8. Register file aur register number (5 bits)
Kyun yeh chahiye: parent stress karta hai ki destination register number (5 bits) ID/EX → EX/MEM → MEM/WB ke saath ride karna chahiye, warna WB galat register mein likhega. Woh "5" ka answer hai.
9. Control signals — sticky notes
Parent inhe teen bundles mein group karta hai is hisaab se ki kaunsa stage unhe use karta hai:
| Bundle | Signals | Use hota hai | Width |
|---|---|---|---|
| EX | ALUSrc, ALUOp, RegDst | EX | |
| MEM | MemRead, MemWrite, Branch | MEM | |
| WB | RegWrite, MemtoReg | WB |
Kyun yeh chahiye: control signals ID mein paida hote hain par baad mein consume hote hain, toh inhe pipeline registers ke andar store kiya jaana chahiye aur aage carry kiya jaana chahiye, har stage par apna bundle drop karte hue. Yahi parent ka central mechanism hai — dekho Control unit design.
10. Widths jodhna — kyun ek register exactly utna hi wide hota hai jitna uska cargo
Kyun yeh chahiye: yeh bas wires ginna hai (Section 2) har cargo item ke across. Addition hi ek tool hai kyunki wires ki bus ke baad wires ki bus wires ki bus hai — kuch aur subtle nahi ho raha.
Yeh foundations topic ko kaise feed karte hain
Equipment checklist
Self-test: right side cover karo aur reveal karne se pehle har ek ka jawab do.
Ek single signal wire par sirf do values kya ho sakti hain?
Ek 32-bit bus mein kitni wires hoti hain?
ka kya matlab hai?
Combinational logic cycles ke beech value hold kyun nahi kar sakta?
Rising clock edge par ek register ke saath exactly kya hota hai?
Paanch stages order mein bolo.
Chaar pipeline registers kyun hain, paanch kyun nahi?
Opcode kaunse stage mein visible hai, aur yeh kyun matter karta hai?
Register number exactly 5 bits kyun hota hai?
Pipeline register ki width kaise compute karte hain?
Connections
- Pipeline registers and control signals (Hinglish) — woh parent topic jise yeh foundations unlock karte hain
- Single-cycle datapath — jahan combinational logic aur paanch stages pehli baar ek lambe path ke roop mein appear hote hain
- Clocking and edge-triggered flip-flops — clock edge aur register ki gehri kahani
- Control unit design — kaise opcode control signals banta hai
- Pipeline hazards — kya galat hota hai jab results aur signals in registers mein stagger ho jaate hain
- Forwarding and stalling — woh fixes jo seedha inhi pipeline registers se padhte hain