Exercises — Pipeline registers and control signals

There are four pipeline registers (a wall sits between neighbouring stages, so 5 stages give 4 gaps):

• IF/ID — between Fetch and Decode
• ID/EX — between Decode and Execute
• EX/MEM — between Execute and Memory
• MEM/WB — between Memory and Write-back

There is no register after WB: WB writes into the register file, which is itself stateful storage. So the count is 4, not 5.

Group them by the stage that uses the signal:

• EX bundle (used in Execute): ALUSrc, ALUOp, RegDst
• MEM bundle (used in Memory): MemRead, MemWrite, Branch
• WB bundle (used in Write-back): RegWrite, MemtoReg

So EX consumes 3, MEM consumes 3, WB consumes 2.

All signals are generated in ID (Decode). Only ID reads the opcode; by the time an instruction reaches EX/MEM/WB, the instruction word has been consumed and those stages see only data + already-latched control bits. So the decode happens once, in ID, and the results travel.

RegWrite is decoded in ID but used only in WB (3 stages later). It must survive every intermediate wall:

• Latched into ID/EX (EX doesn't use it → carried).
• Copied into EX/MEM (MEM doesn't use it → carried).
• Copied into MEM/WB (this is the last wall before WB).
• Used in WB to drive the register-file write-enable, writing the result into $t0.

So it lives in ID/EX, EX/MEM, MEM/WB — three registers — and is consumed in WB.

Add each field that a later stage needs (anything not stored is lost when EX moves on): $W_{EX/MEM}=\underset{\text{ALU result}}{\underbrace{32}}+\underset{\text{store data}}{\underbrace{32}}+\underset{\text{branch target}}{\underbrace{32}}+\underset{\text{Zero}}{\underbrace{1}}+\underset{\text{dest reg \#}}{\underbrace{5}}+\underset{|MEM|}{\underbrace{3}}+\underset{|WB|}{\underbrace{2}}$ $W_{EX/MEM}=32+32+32+1+5+3+2=107\text{bits.}$

$W_{MEM/WB}=\underset{\text{mem data}}{\underbrace{32}}+\underset{\text{ALU result}}{\underbrace{32}}+\underset{\text{dest reg \#}}{\underbrace{5}}+\underset{|WB|}{\underbrace{2}}=71\text{bits.}$ Note MEM/WB is narrower than EX/MEM (71 < 107): it dropped the MEM bundle, the store data, the branch target, and the Zero flag — none of those are used in WB.

When lw's result reaches WB, the lw instruction was fetched 4 cycles ago; IF/ID now holds a different, younger instruction. Bits 20–16 of that instruction are some unrelated register number. So WB would write the loaded word into the wrong register — not $s0.

The fix (correct design): decode the 5-bit destination in ID and latch it ID/EX → EX/MEM → MEM/WB, so WB uses the older instruction's own target. See the dest-# chip travelling all the way to WB in the figure above.

The branch target is computed by an adder in EX: $\text{branch target}=(\text{PC}+4)+(\text{imm}\ll 2).$ The value $\text{PC}+4$ is generated in Fetch but needed in EX. If it only lived in IF/ID, it would be gone by EX and the target adder would have no first operand. So PC+4 rides IF/ID → ID/EX (→ EX/MEM if the branch is resolved in MEM), exactly like any other value produced early and consumed late.

Sizes: $|EX|=3$, $|MEM|=3$, $|WB|=2$.

• ID/EX holds EX+MEM+WB $=3+3+2=8$ control bits.
• EX/MEM holds MEM+WB $=3+2=5$ control bits (EX bundle consumed & dropped).
• MEM/WB holds WB $=2$ control bits (MEM bundle consumed & dropped).

$8>5>2$: strictly decreasing, because each register drops the bundle just used. See the shrinking chip-stack in the figure.

Count how many registers each bundle lives in:

• EX bundle (3 bits): stored only in ID/EX (consumed in EX) → $3\times 1=3$.
• MEM bundle (3 bits): stored in ID/EX and EX/MEM (consumed in MEM) → $3\times 2=6$.
• WB bundle (2 bits): stored in ID/EX, EX/MEM, MEM/WB (consumed in WB) → $2\times 3=6$.

Total control flip-flops $=3+6+6=15$ bits.

Cross-check with the per-register sums: $8+5+2=15$. ✓

$W_{ID/EX}=\underset{\text{RegA}}{\underbrace{32}}+\underset{\text{RegB}}{\underbrace{32}}+\underset{\text{sign-ext imm}}{\underbrace{32}}+\underset{\text{PC+4}}{\underbrace{32}}+\underset{\text{dest reg \#}}{\underbrace{5}}+\underset{\text{EX+MEM+WB}}{\underbrace{8}}$ $W_{ID/EX}=32+32+32+32+5+8=141\text{bits.}$ This is the widest of the pipeline registers — it stands right after decode and carries everything the downstream stages will ever need.

First IF/ID: $W_{IF/ID}=\underset{\text{instruction}}{\underbrace{32}}+\underset{\text{PC+4}}{\underbrace{32}}=64\text{bits.}$ Grand total: $W_{total}=64+141+107+71=383\text{bits}$ of edge-triggered storage just for the pipeline registers (data + control), independent of the register file and memories.

MulEnable is decoded in ID (opcode-derived, like all control) and consumed in EX. It must be preserved from ID until EX, i.e. latched into ID/EX only (1 bit). Since EX consumes it, it is dropped and never enters EX/MEM.

• ID/EX grows by 1 bit ($141\to 142$).
• EX/MEM, MEM/WB: unchanged.

This mirrors the existing EX bundle: born in ID, carried one wall, dropped after use.

It must survive from ID until its last use (WB). So it is latched in ID/EX, EX/MEM, and MEM/WB — the same span as a WB-only signal, because "how far it travels" is set by its latest consumer, not by how many stages read it.

• Flip-flop cost: $1\times 3=3$ bits (one per register it passes through).
• A WB-only signal costs the same 3 bits. Being read in MEM as well adds no storage — the wire is simply tapped in MEM en route.

Key principle: transport cost depends only on the last stage that needs the signal.

Storage compare: carrying a 6-bit opcode in each of ID/EX, EX/MEM, MEM/WB costs $6\times 3=18$ bits — more than the standard 15 bits. So it doesn't even save flip-flops here. Correctness: it can be made to work (each stage re-decodes its own bundle from the carried opcode), but it duplicates the control-unit decode logic into every stage, adding combinational delay to each stage's critical path and complicating verification. The standard design decodes once in ID and merely transports the results — cheaper in bits and in logic. Verdict: the lazy scheme is worse on both axes (18 > 15 bits, plus replicated decoders). The classic "decode once, transport" wins.

• 4 registers, storing 383 bits total for 32-bit MIPS (64 + 141 + 107 + 71).
• Control is decoded once in ID; 15 control flip-flops total across ID/EX (8), EX/MEM (5), MEM/WB (2).
• A signal's storage span is set by its latest consumer; each register drops consumed bundles, so control width strictly shrinks $8>5>2$.