Exercises — Pipeline registers and control signals

Char pipeline registers hain (ek wall neighbouring stages ke beech hoti hai, toh 5 stages se 4 gaps milte hain):

• IF/ID — Fetch aur Decode ke beech
• ID/EX — Decode aur Execute ke beech
• EX/MEM — Execute aur Memory ke beech
• MEM/WB — Memory aur Write-back ke beech

WB ke baad koi register nahi hai: WB register file mein likhta hai, jo khud stateful storage hai. Toh count hai 4, 5 nahi.

Inhe us stage ke hisaab se group karo jo signal use karti hai:

• EX bundle (Execute mein use hota hai): ALUSrc, ALUOp, RegDst
• MEM bundle (Memory mein use hota hai): MemRead, MemWrite, Branch
• WB bundle (Write-back mein use hota hai): RegWrite, MemtoReg

Toh EX 3 consume karta hai, MEM 3, aur WB 2.

Saare signals ID (Decode) mein generate hote hain. Sirf ID opcode padhta hai; jab tak ek instruction EX/MEM/WB tak pahunchti hai, instruction word consume ho chuka hota hai aur woh stages sirf data + already-latched control bits dekhti hain. Toh decode ek baar hota hai, ID mein, aur results travel karte hain.

RegWrite ID mein decode hota hai lekin use sirf WB mein hota hai (3 stages baad). Ise har intermediate wall se guzarna hoga:

• ID/EX mein latch hota hai (EX use nahi karta → carried).
• EX/MEM mein copy hota hai (MEM use nahi karta → carried).
• MEM/WB mein copy hota hai (WB se pehle yeh last wall hai).
• WB mein use hota hai register-file write-enable drive karne ke liye, result $t0 mein likhne ke liye.

Toh yeh ID/EX, EX/MEM, MEM/WB — teen registers — mein rehta hai aur WB mein consume hota hai.

Har woh field add karo jo baad ki stage ko chahiye (jo store nahi hua wo EX ke aage jane par kho jaata hai): $W_{EX/MEM}=\underset{\text{ALU result}}{\underbrace{32}}+\underset{\text{store data}}{\underbrace{32}}+\underset{\text{branch target}}{\underbrace{32}}+\underset{\text{Zero}}{\underbrace{1}}+\underset{\text{dest reg \#}}{\underbrace{5}}+\underset{|MEM|}{\underbrace{3}}+\underset{|WB|}{\underbrace{2}}$ $W_{EX/MEM}=32+32+32+1+5+3+2=107\text{bits.}$

$W_{MEM/WB}=\underset{\text{mem data}}{\underbrace{32}}+\underset{\text{ALU result}}{\underbrace{32}}+\underset{\text{dest reg \#}}{\underbrace{5}}+\underset{|WB|}{\underbrace{2}}=71\text{bits.}$ Note karo ki MEM/WB, EX/MEM se narrower hai (71 < 107): isne MEM bundle, store data, branch target, aur Zero flag drop kar diya — woh sab WB mein use nahi hote.

Jab lw ka result WB tak pahunchta hai, lw instruction 4 cycles pehle fetch hui thi; IF/ID ab ek alag, younger instruction hold karta hai. Us instruction ke bits 20–16 koi unrelated register number hain. Toh WB loaded word ko galat register mein likhega — $s0 mein nahi.

Fix (correct design): 5-bit destination ko ID mein decode karo aur ID/EX → EX/MEM → MEM/WB tak latch karo, taaki WB sahi, purani instruction ka apna target use kare. Figure mein upar dest-# chip ko WB tak travel karte dekho.

Branch target EX mein ek adder se compute hota hai: $\text{branch target}=(\text{PC}+4)+(\text{imm}\ll 2).$ Value $\text{PC}+4$ Fetch mein generate hoti hai lekin EX mein chahiye hoti hai. Agar yeh sirf IF/ID mein rehta, toh EX tak aate aate gone ho jaata aur target adder ka pehla operand hi nahi hota. Toh PC+4 IF/ID → ID/EX (→ EX/MEM agar branch MEM mein resolve ho) ride karta hai, bilkul kisi bhi doosri value ki tarah jo early produce aur late consume hoti hai.

Sizes: $|EX|=3$, $|MEM|=3$, $|WB|=2$.

• ID/EX mein EX+MEM+WB $=3+3+2=8$ control bits hain.
• EX/MEM mein MEM+WB $=3+2=5$ control bits hain (EX bundle consumed & dropped).
• MEM/WB mein WB $=2$ control bits hain (MEM bundle consumed & dropped).

$8>5>2$: strictly decreasing, kyunki har register woh bundle drop karta hai jo abhi use hua. Figure mein shrinking chip-stack dekho.

Count karo ki har bundle kitne registers mein rehti hai:

• EX bundle (3 bits): sirf ID/EX mein store hoti hai (EX mein consume hoti hai) → $3\times 1=3$.
• MEM bundle (3 bits): ID/EX aur EX/MEM mein store hoti hai (MEM mein consume hoti hai) → $3\times 2=6$.
• WB bundle (2 bits): ID/EX, EX/MEM, MEM/WB mein store hoti hai (WB mein consume hoti hai) → $2\times 3=6$.

Total control flip-flops $=3+6+6=15$ bits.

Per-register sums se cross-check: $8+5+2=15$. ✓

$W_{ID/EX}=\underset{\text{RegA}}{\underbrace{32}}+\underset{\text{RegB}}{\underbrace{32}}+\underset{\text{sign-ext imm}}{\underbrace{32}}+\underset{\text{PC+4}}{\underbrace{32}}+\underset{\text{dest reg \#}}{\underbrace{5}}+\underset{\text{EX+MEM+WB}}{\underbrace{8}}$ $W_{ID/EX}=32+32+32+32+5+8=141\text{bits.}$ Yeh pipeline registers mein sabse wide hai — yeh decode ke baad directly khada hai aur sab kuch carry karta hai jo downstream stages ko kabhi bhi chahiye hoga.

Pehle IF/ID: $W_{IF/ID}=\underset{\text{instruction}}{\underbrace{32}}+\underset{\text{PC+4}}{\underbrace{32}}=64\text{bits.}$ Grand total: $W_{total}=64+141+107+71=383\text{bits}$ edge-triggered storage sirf pipeline registers ke liye (data + control), register file aur memories ke alawa.

MulEnable ID mein decode hota hai (opcode-derived, sabhi control ki tarah) aur EX mein consume hota hai. Ise ID se EX tak preserve karna hoga, yaani sirf ID/EX mein latch hoga (1 bit). Kyunki EX use consume karta hai, yeh drop ho jaata hai aur EX/MEM mein kabhi nahi jaata.

• ID/EX 1 bit se bada hoga ($141\to 142$).
• EX/MEM, MEM/WB: unchanged.

Yeh existing EX bundle jaisa hi hai: ID mein paida, ek wall carry, use ke baad drop.

Ise ID se apne last use (WB) tak survive karna hai. Toh yeh ID/EX, EX/MEM, aur MEM/WB mein latched hoga — WB-only signal jaisi hi span, kyunki "kitna far travel karta hai" uske latest consumer se set hota hai, na ki kitni stages padhti hain se.

• Flip-flop cost: $1\times 3=3$ bits (ek per register jisse guzarta hai).
• WB-only signal bhi wahi 3 bits cost karta hai. MEM mein bhi padhna koi extra storage nahi add karta — wire simply MEM mein tap hota hai raaste mein.

Key principle: transport cost sirf last stage par depend karta hai jo signal chahti hai.

Storage compare: ID/EX, EX/MEM, MEM/WB mein se har ek mein 6-bit opcode carry karna $6\times 3=18$ bits cost karta hai — standard 15 bits se zyaada. Toh yeh flip-flops bhi nahi bachata. Correctness: ise kaam karaya ja sakta hai (har stage carried opcode se apna bundle re-decode kare), lekin yeh control-unit decode logic ko har stage mein duplicate karta hai, har stage ke critical path mein combinational delay add karta hai aur verification complicated ho jaati hai. Standard design ID mein ek baar decode karta hai aur sirf results transport karta hai — bits aur logic dono mein sasta. Verdict: lazy scheme dono axes pe worse hai (18 > 15 bits, plus replicated decoders). Classic "decode once, transport" jeetta hai.

• 4 registers, 32-bit MIPS ke liye total 383 bits store karte hain (64 + 141 + 107 + 71).
• Control ID mein ek baar decode hota hai; ID/EX (8), EX/MEM (5), MEM/WB (2) mein total 15 control flip-flops hain.
• Ek signal ki storage span uske latest consumer se set hoti hai; har register consumed bundles drop karta hai, toh control width strictly shrink hoti hai $8>5>2$.