Multi-cycle datapath: Question bank — Hardware deep dive

True or false — justify

Each prompt: state True/False and the reason. A bare T/F earns nothing.

True or false: In multi-cycle, the clock period is set by the whole lw path (fetch→...→write-back).

False — the clock only has to fit the longest single step, not the whole instruction; that is exactly why multi-cycle shortens the clock.

True or false: A single unified memory is enough for both instructions and data in a multi-cycle CPU.

True — instruction fetch (IF) and data access (MEM) happen in different cycles, so one memory never has to serve both roles at once.

True or false: Every instruction takes exactly 5 cycles because there are 5 steps.

False — an instruction ends the moment its work is done; beq/j finish in 3, R-type and sw in 4, only lw uses all 5.

True or false: The ALU is used in only one cycle per instruction.

False — it computes PC+4 in IF, the branch target in ID, and the real operation in EX, so it can work in three different cycles with different operands.

True or false: R-type instructions write their result during the MEM step.

False — R-type has no memory access, skips MEM entirely, and writes ALUOut to the register file in the WB step (its 4th cycle).

True or false: Computing the branch target in ID is wasted work when the instruction turns out to be add.

True but cheap — the ALU is idle in ID anyway, so speculatively computing the target costs nothing extra and saves a cycle when the instruction is a branch.

True or false: Multi-cycle is always faster in raw execution time than single-cycle.

False — execution time = cycles × period; if one stage is unbalanced (e.g. ID = 300 ps) the extra cycles can cancel or beat the shorter clock, so it can be slower on some mixes.

True or false: Internal registers (IR, A, B, ALUOut, MDR) store final architectural results the programmer can read.

False — they are invisible working registers that just pass combinational values across clock edges; they hold nothing the ISA exposes.

True or false: sw needs a WB step.

False — sw writes to memory in MEM and produces no register result, so it finishes at MEM (4 cycles) with no write-back.

True or false: j (jump) could finish in 2 cycles since it does no arithmetic.

False — the PC is updated in the EX step, so the jump must reach EX; it uses IF, ID, EX = 3 cycles.

Spot the error

Each says something almost right — name the flaw.

"Since the ALU is combinational, its EX result is still available in WB, so R-type needs no register to hold it."

The flaw: combinational outputs vanish once inputs change at the clock edge; the EX result must be latched into ALUOut so WB can read it a cycle later.

"beq compares A and B in ID, right after they're read."

The flaw: A and B are only fetched in ID; the comparison (subtraction) happens in EX, and the target — computed in ID — is loaded into PC there.

"Multi-cycle removes hardware by having a separate ALU for PC increment and for arithmetic."

The flaw: it does the opposite — it shares one ALU across IF/ID/EX by using multiplexers to select operands each cycle; separate ALUs would add hardware.

"lw finishes in MEM because that's where the data is fetched."

The flaw: MEM fetches data into MDR, but the value still must be written into the register file in WB, so lw needs the 5th cycle.

"The clock period equals the sum of all step delays."

The flaw: it equals the maximum single-step delay, not the sum — steps happen in separate cycles, not stacked in one.

"Because ID reads registers, it must be the fastest stage."

The flaw: in the parent's numbers ID does a register read followed by an ALU branch-target op in the same cycle (100+200=300 ps), making it the slowest stage.

"Since add uses fewer cycles than lw, add must run faster in multi-cycle than in single-cycle."

The flaw: add = 4×300 = 1200 ps in multi-cycle but only 800 ps single-cycle; fewer cycles than lw doesn't mean faster than its own single-cycle time.

Why questions

Why do we latch the fetched bits into IR instead of reading memory again in later cycles?

Because the same memory is reused for data in a later cycle, so the instruction bits would be overwritten/lost; IR keeps them sticky until decode and beyond.

Why compute PC+4 during IF rather than in a dedicated cycle?

The ALU (or a small adder) is free during fetch, so incrementing PC there reuses idle hardware and avoids spending an extra cycle.

Why is the branch target computed in ID before we even know the instruction is a branch?

It's optimistic pre-computation — the ALU is idle in ID, so doing it early is free and saves a cycle if the instruction really is beq.

Why does multi-cycle need internal registers but single-cycle doesn't?

Single-cycle passes signals through in one continuous combinational sweep; multi-cycle spreads work across clock edges, so results must be stored between cycles to survive.

Why can sw skip the WB step but lw cannot?

sw sends data to memory and produces no register result, while lw brings a value from memory that still has to be written into a register.

Why is "compare clock speeds" a wrong way to rank multi-cycle vs single-cycle?

Speed of one instruction depends on cycles × period; a shorter period with more cycles can lose, so only total execution time (over a real instruction mix) is a fair comparison.

Why does the guaranteed benefit of multi-cycle come from hardware, not always speed?

Speed depends on how balanced the stages are (unbalanced ID can erase the gain), but the sharing of one memory and one ALU always reduces hardware cost.

Edge cases

What happens in the MEM step for an R-type instruction?

Nothing — R-type has no memory work, so it never enters MEM; its 4th cycle is WB instead.

For beq where the branch is not taken, what does EX do to the PC?

It leaves the PC alone at the already-loaded PC+4 (from IF); only a taken branch loads ALUOut (the target) into PC.

If a stage's delay were 0 (a degenerate "free" step), would the clock period change?

No — the clock is set by the longest stage, so a zero-delay stage is harmless; only the maximum matters.

What is the minimum possible cycle count for any instruction in this design, and which uses it?

3 cycles (IF, ID, EX), used by beq and j, because both settle the PC by the end of EX and need nothing more.

If all five stage delays were made perfectly equal, why would multi-cycle finally beat single-cycle on speed?

Balanced stages mean the clock = one clean fraction of the whole path with no wasted slack, so cycles × period drops below the single-cycle worst-case time.

Could two different instructions ever use the ALU for different purposes in the same cycle?

No — there is only one ALU and one instruction in flight, so each cycle the ALU serves exactly one role selected by multiplexers.

What holds the data between the MEM read and the WB write for a lw?

The MDR (Memory Data Register) catches the loaded value so WB can copy it into the register file one cycle later.

Recall One-line summary of the traps

Multi-cycle wins by shorter clock + hardware reuse, not by being universally faster; each instruction ends when its work is done, and every intermediate value must be latched to survive the clock edge.

See also: Single-cycle datapath, Pipelining, Control unit — FSM vs microprogramming, CPI and CPU performance equation, ALU design, Memory hierarchy.