Multi-cycle datapath: Question bank — Hinglish deep dive

5.2.2 · D5 · Hardware › Processor Datapath & Pipelining › Multi-cycle datapath

True or false — justify

Har prompt ke liye: True/False aur reason batao. Sirf T/F likhne se kuch nahi milega.

True or false: Multi-cycle mein clock period poore lw path (fetch→...→write-back) ke hisaab se set hoti hai.

False — clock ko sirf sabse lamba single step fit karna hota hai, poora instruction nahi; yahi wajah hai ki multi-cycle clock ko chhota karta hai.

True or false: Multi-cycle CPU mein instructions aur data dono ke liye ek hi unified memory kaafi hai.

True — instruction fetch (IF) aur data access (MEM) alag-alag cycles mein hote hain, isliye ek memory ko kabhi bhi dono roles ek saath serve nahi karne padte.

True or false: Har instruction exactly 5 cycles leta hai kyunki 5 steps hain.

False — instruction wahan khatam hoti hai jahan uska kaam ho jaata hai; beq/j 3 mein khatam, R-type aur sw 4 mein, sirf lw saare 5 use karta hai.

True or false: ALU ek instruction mein sirf ek hi cycle mein use hota hai.

False — ye IF mein PC+4 compute karta hai, ID mein branch target, aur EX mein real operation, isliye teen alag cycles mein alag operands ke saath kaam kar sakta hai.

True or false: R-type instructions apna result MEM step mein write karti hain.

False — R-type ka koi memory access nahi hota, ye MEM ko skip karta hai, aur ALUOut ko WB step mein register file mein likhta hai (uska 4th cycle).

True or false: ID mein branch target compute karna wasted work hai jab instruction add nikle.

True but cheap — ALU ID meinaise bhi idle hota hai, isliye speculatively target compute karne mein koi extra cost nahi aur jab instruction actually branch hoti hai toh ek cycle bachti hai.

True or false: Multi-cycle raw execution time mein single-cycle se hamesha faster hota hai.

False — execution time = cycles × period; agar ek stage unbalanced ho (jaise ID = 300 ps) toh extra cycles shorter clock ka faayda khatam kar sakti hain, toh kuch mixes mein ye slower bhi ho sakta hai.

True or false: Internal registers (IR, A, B, ALUOut, MDR) final architectural results store karte hain jo programmer read kar sakta hai.

False — ye invisible working registers hain jo sirf combinational values ko clock edges ke paas pahunaate hain; ye kuch bhi ISA expose nahi karte.

True or false: sw ko WB step ki zaroorat hoti hai.

False — sw MEM mein memory mein likhta hai aur koi register result produce nahi karta, isliye ye MEM par khatam ho jaata hai (4 cycles), koi write-back nahi.

True or false: j (jump) 2 cycles mein khatam ho sakta hai kyunki ye koi arithmetic nahi karta.

False — PC ko EX step mein update kiya jaata hai, isliye jump ko EX tak pahunchna hi padega; ye IF, ID, EX = 3 cycles use karta hai.

Spot the error

Har statement almost sahi hai — galti dhundho.

"Kyunki ALU combinational hai, uska EX result WB mein bhi available hota hai, isliye R-type ko use hold karne ki koi register nahi chahiye."

Galti yeh hai: combinational outputs clock edge par inputs change hote hi gayab ho jaate hain; EX result ko ALUOut mein latch karna zarori hai taaki WB ek cycle baad use padh sake.

"beq, A aur B ko ID mein compare karta hai, unhe read karne ke turant baad."

Galti yeh hai: A aur B sirf ID mein fetch hote hain; comparison (subtraction) EX mein hota hai, aur target — jo ID mein compute hota hai — wahan PC mein load hota hai.

"Multi-cycle hardware remove karta hai — ek alag ALU PC increment ke liye aur ek arithmetic ke liye."

Galti yeh hai: ye bilkul ulta karta hai — ye multiplexers ki madad se IF/ID/EX mein ek ALU share karta hai; alag ALUs hardware badhaa denge.

"lw MEM mein khatam hoti hai kyunki data wahan fetch hota hai."

Galti yeh hai: MEM data ko MDR mein fetch karta hai, lekin value ko WB mein register file mein likhna baaki hota hai, isliye lw ko 5th cycle chahiye.

"Clock period sab step delays ka sum hoti hai."

Galti yeh hai: ye maximum single-step delay ke barabar hoti hai, sum nahi — steps alag cycles mein hote hain, ek hi mein stack nahi.

"Kyunki ID registers read karta hai, ye sabse fast stage honi chahiye."

Galti yeh hai: parent ke numbers mein ID ek register read ke baad same cycle mein ek ALU branch-target op karta hai (100+200=300 ps), jisse ye sabse slow stage ban jaati hai.

"Kyunki add lw se kam cycles use karta hai, add multi-cycle mein single-cycle se faster hoga."

Galti yeh hai: add = 4×300 = 1200 ps multi-cycle mein lekin sirf 800 ps single-cycle mein; lw se kam cycles ka matlab apne single-cycle time se faster nahi hai.

Why questions

Hum fetched bits ko IR mein latch kyun karte hain instead of baad ke cycles mein memory dobara read karne ke?

Kyunki wahi memory baad ke cycle mein data ke liye reuse hoti hai, isliye instruction bits overwrite/lost ho jaate; IR unhe decode aur usse aage tak sticky rakhta hai.

PC+4 IF ke dauran compute kyun karte hain rather than ek dedicated cycle mein?

ALU (ya ek small adder) fetch ke dauran free hota hai, isliye wahan PC increment karna idle hardware reuse karta hai aur ek extra cycle spend karne se bachata hai.

Branch target ko ID mein compute kyun karte hain jab hum jaante bhi nahi ki instruction branch hai?

Ye optimistic pre-computation hai — ALU ID mein idle hai, isliye pehle karna free hai aur ek cycle bachta hai agar instruction actually beq nikle.

Multi-cycle ko internal registers ki zaroorat kyun hai lekin single-cycle ko nahi?

Single-cycle signals ko ek continuous combinational sweep mein paas karta hai; multi-cycle kaam ko clock edges mein spread karta hai, isliye results ko cycles ke beech survive karne ke liye store karna padta hai.

sw WB step skip kyun kar sakta hai lekin lw nahi?

sw data memory ko bhejta hai aur koi register result produce nahi karta, jabki lw memory se ek value laata hai jo ek register mein likhni padti hai.

"Clock speeds compare karna" multi-cycle vs single-cycle rank karne ka galat tarika kyun hai?

Ek instruction ki speed cycles × period par depend karti hai; ek shorter period zyada cycles ke saath haar sakti hai, isliye sirf total execution time (real instruction mix par) fair comparison hai.

Multi-cycle ka guaranteed benefit speed se nahi, hardware se kyun aata hai?

Speed is baat par depend karti hai ki stages kitni balanced hain (unbalanced ID faayda khatam kar sakti hai), lekin ek memory aur ek ALU share karna hamesha hardware cost reduce karta hai.

Edge cases

R-type instruction ke liye MEM step mein kya hota hai?

Kuch nahi — R-type ka koi memory kaam nahi, isliye ye MEM mein kabhi nahi jaata; uska 4th cycle WB hoti hai.

beq mein jahan branch not taken ho, EX PC ke saath kya karta hai?

Ye PC ko already-loaded PC+4 (IF se) par hi rehne deta hai; sirf taken branch ALUOut (target) ko PC mein load karta hai.

Agar kisi stage ki delay 0 hoti (ek degenerate "free" step), toh kya clock period change hoti?

Nahi — clock sabse lamba stage ke hisaab se set hoti hai, isliye zero-delay stage harmless hai; sirf maximum matter karta hai.

Is design mein kisi bhi instruction ke liye minimum possible cycle count kitna hai, aur kaunsa use karta hai?

3 cycles (IF, ID, EX), beq aur j use karte hain, kyunki dono EX ke end tak PC settle kar lete hain aur baad mein kuch nahi chahiye.

Agar saare paanch stage delays perfectly equal kar diye jaayein, toh multi-cycle speed mein single-cycle ko finally kyun beat karta?

Balanced stages ka matlab hai clock = poore path ka ek clean fraction bina kisi wasted slack ke, isliye cycles × period single-cycle worst-case time se neeche aa jaata hai.

Kya do alag instructions kabhi same cycle mein ALU ko alag purposes ke liye use kar sakti hain?

Nahi — ek hi ALU hai aur ek hi instruction in-flight hai, isliye har cycle mein ALU exactly ek role serve karta hai jo multiplexers se select hota hai.

lw ke liye MEM read aur WB write ke beech data kya hold karta hai?

MDR (Memory Data Register) loaded value ko pakadta hai taaki WB ek cycle baad use register file mein copy kar sake.

Recall Traps ki ek-line summary

Multi-cycle shorter clock + hardware reuse se jeetta hai, universally faster hone se nahi; har instruction apna kaam hone par khatam hoti hai, aur har intermediate value ko clock edge survive karne ke liye latch karna padta hai.

See also: Single-cycle datapath, Pipelining, Control unit — FSM vs microprogramming, CPI and CPU performance equation, ALU design, Memory hierarchy.