Foundations — Load - store architecture model

Before you can read the parent note with confidence, you must be able to see every word it throws at you. This page takes the topic apart into its smallest pieces and rebuilds it one picture at a time. We assume you have seen nothing — not "register", not "CPI", not even "instruction". Line one starts from zero.

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1. What is a "computer" made of, for our purposes?

Forget screens and keyboards. For this topic a computer is three boxes and a wire between them.

The wire in the middle is the only path between memory and the shelf. Everything the parent note calls "load/store" is a rule about what may travel on that wire.

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2. Register — the worker's shelf

The picture: a labelled cubby. In MIPS-style code these are written R1, R2, R3, …; in ARM the same idea. When the parent note writes ADD R6, R4, R5, read it as:

"Worker: take the number in cubby R4, take the number in cubby R5, add them, put the answer in cubby R6."

Notice all three names are cubbies, never mailboxes. That is the whole rule of a load/store machine, and we will nail it down in §4.

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3. Memory and the address — the warehouse and its labels

The notation [R0] or 0(R1) means "the mailbox whose number is currently sitting in that register" — the square brackets say "don't use this number itself, go to the mailbox it points at."

The 0 in 0(R1) is an offset — "start at the address in R1, then step 0 mailboxes further." Offsets let one register point at a whole array; that machinery is the topic of Addressing modes.

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4. Load and Store — the only two things allowed on the wire

Here is the heart of the topic, and now every word in it is already defined.

Recall Why forbid arithmetic straight on memory?

Because memory access takes an unpredictable number of ticks (fast if the number is nearby, slow if far — see Memory hierarchy). By quarantining all that unpredictability into just two instruction types, every other instruction becomes fast and takes a fixed, known time. ::: Predictable timing is the reward for the extra instructions.

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5. Instruction and Opcode

The parent note counts instructions with the letter $I$:

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6. Clock, cycle, and frequency

Why the topic needs frequency: simpler instructions (§4's rule) let the chip finish each tick's work faster, so $T_{\text{clk}}$ shrinks and $f_{\text{clk}}$ rises. This is the parent's claim "3 GHz vs 2.5 GHz."

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7. CPI — cycles per instruction

The symbol $\ll$ in the parent ($\text{CPI}_{\text{ls}} \ll \text{CPI}_{\text{rm}}$) just means "is much smaller than."

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8. Putting the performance formula together

Now every letter is earned, so the master equation reads cleanly:

Let us verify the parent's headline numbers with defined symbols only:

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9. Why "many registers" matters (register pressure)

The parent's Example 2 keeps (a+b) and (c+3) alive in cubbies at the same time. If you run out of cubbies you must dump one back to memory (a spill) and reload it later — extra slow trips. That is why load/store machines carry 32 registers, not 8. Choosing which value lives where is Register allocation.

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How the foundations feed the topic

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Equipment checklist

Test yourself — cover the right side of each line and answer aloud.