Exercises — Load - store architecture model

Answer: (c). The single defining rule of a load/store architecture is: only load and store touch memory; the ALU only sees registers. Instruction (c) asks the ADD (an ALU op) to read straight from memory [R2] — that is forbidden.

• (a) is a load — allowed to touch memory. ✓
• (b) is an ALU op on three registers, no memory. ✓
• (d) is a store — allowed to touch memory. ✓
• (c) is an ALU op with a memory operand → illegal here (it is legal on a register-memory machine like x86, which is exactly the contrast the parent note draws).

• ADD [addr], EAX folds a memory read + arithmetic + memory write into one instruction → register-memory (also just "CISC-style memory model").
• The strict load → compute → store separation is the load/store model, also called register-register. See RISC vs CISC philosophy for the wider debate.

The fused instruction does three hidden things: read x, add R5, write x back. Split them out:

LDR  R1, [R10]     ; R1 = memory[x]       (load)
ADD  R1, R1, R5    ; R1 = R1 + R5         (ALU, registers only)
STR  R1, [R10]     ; memory[x] = R1       (store)

One register-memory instruction became three load/store instructions — matching the parent's formula $I_{\text{ls}}=N_{\text{ops}}+N_{\text{loads}}+N_{\text{stores}}=1+1+1=3$.

(a) Load/store keeps everything separate: $I_{\text{ls}}=N_{\text{ops}}+N_{\text{loads}}+N_{\text{stores}}=5+4+2=11.$ (b) Register-memory: 3 fused ops each swallow one memory access, removing 3 separate load/store instructions: $I_{\text{rm}}=11-3=8.$ So the register-memory version runs fewer instructions (8 < 11) — but read the next mistake box before you cheer.

$T_{\text{clk}}=\frac{1}{f_{\text{clk}}}=\frac{1}{3\times 10^9\text{Hz}}=0.333\times 10^{-9}\text{s}=0.333\text{ns}.$ (One tick lasts a third of a nanosecond. This is the "seconds per step" in our master equation.)

Plug into $T=I\times \text{CPI}\times T_{\text{clk}}$: $T_{\text{x86}}=1\times 10\times 0.4\text{ns}=4.0\text{ns}.$ $T_{\text{ARM}}=3\times 4\times 0.333\text{ns}=3.996\approx 4.0\text{ns}.$ They tie at ≈4.0 ns. The extra ARM instructions ($3>1$) are exactly cancelled by its lower CPI ($4<10$) and higher clock ($3\text{GHz}>2.5\text{GHz}$). This is the whole point of the parent note: load/store trades more instructions for lower CPI and higher clock. In real silicon the tie usually tips ARM's way once Instruction pipelining hides the load latency.

CPI is total cycles divided by instruction count: ${\text{CPI}}_{\text{ARM}}=\frac{\text{total cycles}}{\text{instructions}}=\frac{12}{3}=4.$ The x86 fused ADD [addr], EAX cannot overlap its internal read → modify → write; the whole ~10-cycle memory latency is exposed as one indivisible instruction: ${\text{CPI}}_{\text{x86}}=\frac{10}{1}=10.$ Key insight: ARM's win is not fewer cycles per memory access — it is that pipelining lets other instructions run during the miss, so the average per-instruction cost falls.

New CPI: ${\text{CPI}}_{\text{ARM}}=\frac{9}{3}=3.$ New time: $T_{\text{ARM}}=3\times 3\times 0.333\text{ns}=3.0\text{ns}.$ Now $3.0\text{ns}<4.0\text{ns}$: ARM wins. Better latency hiding (deeper/smarter pipelining, out-of-order issue) directly lowers CPI and hence total time, even though instruction count $I=3$ never changed.

LDR  R1, [R10]     ; R1 = a
LDR  R2, [R11]     ; R2 = b
ADD  R3, R1, R2    ; R3 = a + b        (intermediate 1)
LDR  R4, [R12]     ; R4 = c
ADD  R5, R4, #3    ; R5 = c + 3        (intermediate 2)
MUL  R6, R3, R5    ; R6 = (a+b)(c+3)
STR  R6, [R13]     ; d = R6

Busiest moment: just before the MUL, both partial results must be alive at once — R3 = a+b and R5 = c+3. That is 2 live intermediates. This is why load/store ISAs ship many registers (32 in RISC-V/MIPS): intermediates live in registers instead of spilling to memory. See Register allocation.

• Loads: LDR R1, LDR R2, LDR R4 → $N_{\text{loads}}=3$.
• Stores: STR R6 → $N_{\text{stores}}=1$.
• ALU ops: ADD, ADD, MUL → $N_{\text{ops}}=3$.
• Total lines: $I=7$. Check: $N_{\text{ops}}+N_{\text{loads}}+N_{\text{stores}}=3+3+1=7=I.$ ✓

With 2 registers you compute a+b first, but you have nowhere to keep it while you compute c+3, so you store it to [SP], do the second sum, then load it back for the multiply:

LDR  R1, [R10]     ; a
LDR  R2, [R11]     ; b
ADD  R1, R1, R2    ; R1 = a+b
STR  R1, [SP]      ; SPILL a+b to memory      <-- extra store
LDR  R1, [R12]     ; c
ADD  R1, R1, #3    ; R1 = c+3
LDR  R2, [SP]      ; RELOAD a+b                <-- extra load
MUL  R1, R2, R1    ; product
STR  R1, [R13]     ; d

Extra instructions vs L4.1: one store + one load = 2 extra. This is the concrete cost of too few registers, and precisely why load/store designs favour large register files. See Register allocation and Memory hierarchy.

Choose load/store. Its arithmetic instructions have fixed, low CPI (they never touch memory), and memory latency is isolated into explicit loads/stores you can bound separately — so every instruction's worst-case cycle cost is predictable, which is exactly what a provable real-time deadline needs. A register-memory ADD [addr] hides variable cache latency inside an arithmetic instruction, making its CPI (and thus its slice of $T$) unpredictable.

When instruction-fetch bandwidth or code size is the bottleneck — e.g. a memory-constrained embedded device, or a workload where the instruction cache thrashes. Fewer, denser instructions ($I_{\text{rm}}<I_{\text{ls}}$) mean fewer bytes to fetch and store, easing pressure on the Memory hierarchy and Instruction encoding. This is a large part of why x86's dense CISC encoding survived: legacy code density and I-cache footprint. The trade lives in the same equation — you accept a higher CPI to shrink $I$ and the fetch traffic.

Notice $I\times \text{CPI}=3\times (C/3)=C$ — the total cycle count is the product. So: $T_{\text{ARM}}=C\times T_{\text{clk}}=C\times 0.333\text{ns}.$ Set equal to x86: $C\times 0.333\text{ns}=4.0\text{ns}\Rightarrow C=\frac{4.0}{0.333}=12.$ So 12 cycles is exactly the tie point — matching L3.2. Any pipeline improvement that gets ARM below 12 total cycles (e.g. L3.3's 9 cycles) makes load/store the winner; anything above 12 loses.

Only load and store touch memory in a load/store ISA ::: True — the defining rule. Formula for load/store instruction count ::: $I_{\text{ls}}=N_{\text{ops}}+N_{\text{loads}}+N_{\text{stores}}$. Master timing equation ::: $T=I\times \text{CPI}\times T_{\text{clk}}=I\times \text{CPI}/f_{\text{clk}}$. $T_{\text{clk}}$ at 3 GHz ::: $0.333\text{ns}$. Why load/store can tie x86 despite more instructions ::: lower CPI and higher clock cancel the larger $I$. Cost of too few registers ::: register spilling adds extra store+load instructions.