Exercises — Load - store architecture model

Answer: (c). Ek load/store architecture ka ek hi defining rule hai: sirf load aur store memory ko touch karte hain; ALU sirf registers dekhta hai. Instruction (c) ADD (ek ALU op) se seedha memory [R2] padhne ko keh raha hai — yeh forbidden hai.

• (a) ek load hai — memory touch karna allowed. ✓
• (b) ek ALU op hai teen registers par, koi memory nahi. ✓
• (d) ek store hai — memory touch karna allowed. ✓
• (c) ek ALU op hai memory operand ke saath → yahan illegal (yeh x86 jaise register-memory machine par legal hai, jo exactly woh contrast hai jo parent note draw karta hai).

• ADD [addr], EAX ek memory read + arithmetic + memory write ko ek instruction mein fold karta hai → register-memory (ise "CISC-style memory model" bhi kehte hain).
• Strict load → compute → store separation load/store model hai, jise register-register bhi kehte hain. Wider debate ke liye RISC vs CISC philosophy dekho.

Yeh fused instruction teen hidden cheezein karti hai: x padho, R5 add karo, x wapas likho. Inhe alag karo:

LDR  R1, [R10]     ; R1 = memory[x]       (load)
ADD  R1, R1, R5    ; R1 = R1 + R5         (ALU, sirf registers)
STR  R1, [R10]     ; memory[x] = R1       (store)

Ek register-memory instruction teen load/store instructions ban gayi — parent ke formula se match karta hai $I_{\text{ls}}=N_{\text{ops}}+N_{\text{loads}}+N_{\text{stores}}=1+1+1=3$.

(a) Load/store sab kuch alag rakhta hai: $I_{\text{ls}}=N_{\text{ops}}+N_{\text{loads}}+N_{\text{stores}}=5+4+2=11.$ (b) Register-memory: 3 fused ops mein se har ek ek memory access nigal leta hai, 3 alag load/store instructions hata ke: $I_{\text{rm}}=11-3=8.$ To register-memory version kam instructions run karta hai (8 < 11) — lekin agle mistake box padho khush hone se pehle.

$T_{\text{clk}}=\frac{1}{f_{\text{clk}}}=\frac{1}{3\times 10^9\text{Hz}}=0.333\times 10^{-9}\text{s}=0.333\text{ns}.$ (Ek tick ek nanosecond ka teesra hissa rehta hai. Yeh hamare master equation mein "seconds per step" hai.)

$T=I\times \text{CPI}\times T_{\text{clk}}$ mein plug karo: $T_{\text{x86}}=1\times 10\times 0.4\text{ns}=4.0\text{ns}.$ $T_{\text{ARM}}=3\times 4\times 0.333\text{ns}=3.996\approx 4.0\text{ns}.$ Dono tie karte hain ≈4.0 ns par. Extra ARM instructions ($3>1$) exactly cancel ho jaati hain uske lower CPI ($4<10$) aur higher clock ($3\text{GHz}>2.5\text{GHz}$) se. Yahi parent note ka poora point hai: load/store trade karta hai zyaada instructions ko lower CPI aur higher clock ke liye. Real silicon mein yeh tie usually ARM ki taraf tip karta hai jab Instruction pipelining load latency hide kar leta hai.

CPI total cycles ko instruction count se divide karna hai: ${\text{CPI}}_{\text{ARM}}=\frac{\text{total cycles}}{\text{instructions}}=\frac{12}{3}=4.$ x86 ka fused ADD [addr], EAX apna internal read → modify → write overlap nahi kar sakta; poori ~10-cycle memory latency ek indivisible instruction ke roop mein expose hoti hai: ${\text{CPI}}_{\text{x86}}=\frac{10}{1}=10.$ Key insight: ARM ki jeet yeh nahi hai ki har memory access ke fewer cycles hain — yeh hai ki pipelining doosre instructions ko miss ke dauran run karne deta hai, to average per-instruction cost gir jaati hai.

Naya CPI: ${\text{CPI}}_{\text{ARM}}=\frac{9}{3}=3.$ Naya time: $T_{\text{ARM}}=3\times 3\times 0.333\text{ns}=3.0\text{ns}.$ Ab $3.0\text{ns}<4.0\text{ns}$: ARM jeetta hai. Better latency hiding (deeper/smarter pipelining, out-of-order issue) directly CPI aur isliye total time kam karta hai, even though instruction count $I=3$ kabhi nahi badla.

LDR  R1, [R10]     ; R1 = a
LDR  R2, [R11]     ; R2 = b
ADD  R3, R1, R2    ; R3 = a + b        (intermediate 1)
LDR  R4, [R12]     ; R4 = c
ADD  R5, R4, #3    ; R5 = c + 3        (intermediate 2)
MUL  R6, R3, R5    ; R6 = (a+b)(c+3)
STR  R6, [R13]     ; d = R6

Sabse busy moment: MUL se thoda pehle, dono partial results ek saath alive hone chahiye — R3 = a+b aur R5 = c+3. Yeh 2 live intermediates hain. Isi liye load/store ISAs mein bahut saare registers hote hain (RISC-V/MIPS mein 32): intermediates memory mein spill karne ki jagah registers mein rahte hain. Register allocation dekho.

• Loads: LDR R1, LDR R2, LDR R4 → $N_{\text{loads}}=3$.
• Stores: STR R6 → $N_{\text{stores}}=1$.
• ALU ops: ADD, ADD, MUL → $N_{\text{ops}}=3$.
• Total lines: $I=7$. Check: $N_{\text{ops}}+N_{\text{loads}}+N_{\text{stores}}=3+3+1=7=I.$ ✓

2 registers ke saath tum pehle a+b compute karte ho, lekin jab c+3 compute karo tab usse rakhne ki jagah nahi hai, to tum usse [SP] par store karte ho, doosra sum karte ho, phir multiply ke liye usse wapas load karte ho:

LDR  R1, [R10]     ; a
LDR  R2, [R11]     ; b
ADD  R1, R1, R2    ; R1 = a+b
STR  R1, [SP]      ; a+b ko memory mein SPILL karo      <-- extra store
LDR  R1, [R12]     ; c
ADD  R1, R1, #3    ; R1 = c+3
LDR  R2, [SP]      ; a+b RELOAD karo                    <-- extra load
MUL  R1, R2, R1    ; product
STR  R1, [R13]     ; d

L4.1 ke comparison mein extra instructions: ek store + ek load = 2 extra. Yeh hai concrete cost bahut kam registers ki, aur precisely isi liye load/store designs large register files prefer karte hain. Register allocation aur Memory hierarchy dekho.

Load/store choose karo. Iske arithmetic instructions ka fixed, low CPI hota hai (woh kabhi memory touch nahi karte), aur memory latency explicit loads/stores mein isolate hoti hai jise tum alag se bound kar sakte ho — isliye har instruction ka worst-case cycle cost predictable hota hai, jo exactly woh cheez hai jo ek provable real-time deadline ko chahiye. Ek register-memory ADD [addr] variable cache latency ko ek arithmetic instruction ke andar chhupaata hai, jisse uska CPI (aur isliye $T$ ka uska hissa) unpredictable ho jaata hai.

Jab instruction-fetch bandwidth ya code size bottleneck ho — jaise ek memory-constrained embedded device, ya aisa workload jahan instruction cache thrash kare. Kam, denser instructions ($I_{\text{rm}}<I_{\text{ls}}$) matlab fetch aur store karne ke liye fewer bytes, Memory hierarchy aur Instruction encoding par pressure kam. Yeh ek bada part hai kyun x86 ki dense CISC encoding survive ki: legacy code density aur I-cache footprint. Yeh trade-off usi equation mein rehta hai — tum higher CPI accept karte ho $I$ aur fetch traffic shrink karne ke liye.

Note karo ki $I\times \text{CPI}=3\times (C/3)=C$ — total cycle count hi woh product hai. To: $T_{\text{ARM}}=C\times T_{\text{clk}}=C\times 0.333\text{ns}.$ x86 ke barabar set karo: $C\times 0.333\text{ns}=4.0\text{ns}\Rightarrow C=\frac{4.0}{0.333}=12.$ To 12 cycles exactly tie point hai — L3.2 se match karta hai. Koi bhi pipeline improvement jo ARM ko 12 total cycles se neeche laaye (jaise L3.3 ke 9 cycles) load/store ko winner banata hai; 12 se upar kuch bhi lose karta hai.

Load/store ISA mein sirf load aur store memory touch karte hain ::: True — defining rule. Load/store instruction count ka formula ::: $I_{\text{ls}}=N_{\text{ops}}+N_{\text{loads}}+N_{\text{stores}}$. Master timing equation ::: $T=I\times \text{CPI}\times T_{\text{clk}}=I\times \text{CPI}/f_{\text{clk}}$. $T_{\text{clk}}$ 3 GHz par ::: $0.333\text{ns}$. Load/store zyaada instructions ke bawajood x86 se tie kyun kar sakta hai ::: lower CPI aur higher clock bade $I$ ko cancel kar dete hain. Bahut kam registers ki cost ::: register spilling extra store+load instructions add karta hai.