5.1.9 · D1Load - store architecture model
Intuition Is poore topic ke peeche ek hi idea haiEk load/store computer memory (numbers ka ek bahut bada, lekin slow warehouse) aur mutthi bhar chhote, fast registers ke beech ek pakki diwar banaye rakhta hai — jahan par actual arithmetic hoti hai. Parent note mein jo bhi hai — instruction counts, cycles, clock speed, pipelining — sab usi hisaab-kitaab ke baare mein hai ki numbers us diwar ko kaise cross karte hain.
Pehle aapko parent note confident hokar padh paana chahiye, matlab aapko har wo shabd "dekhna" aana chahiye jo woh aap par fenkta hai. Ye page is topic ko uske sabse chhote tukdon mein tod ke, ek ek picture ke saath wapas jodata hai. Hum maan rahe hain aapne kuch nahi dekha — na "register", na "CPI", aur na hi "instruction". Pehli line zero se shuru hoti hai.
Screens aur keyboards bhool jao. Is topic ke liye ek computer teen boxes aur unke beech ek wire hai.
Memory — numbered mailboxes ki ek bahut lambi row. Har mailbox ek number hold karta hai. Inki sankhya billions mein hai, isliye yeh bada hai, lekin kisi door wale mailbox tak pahunchna slow hai.Registers — worker ke bilkul paas ek chhoti si shelf, shayad 8 se 32 numbers rakhti hai. Chhoti hai, lekin pahuchchna instant hai.ALU (Arithmetic-Logic Unit) — "worker": akela hissa jo actually add, subtract, multiply, compare kar sakta hai.
Beech mein wire memory aur shelf ke beech ka akela raasta hai. Jo kuch bhi parent note "load/store" kehta hai, woh ek rule hai ki us wire par kya travel kar sakta hai .
Intuition Do tarah ki storage kyun hoti hai?Physics yeh trade-off force karta hai. Jo store ek clock tick mein readable ho, woh chhota hona chahiye (registers). Jo store poora program hold karne ke liye kaafi bada ho, woh chip par door hoga aur pohonchne mein kaafi ticks lagenge (memory). "Bada aur instant" nahi ho sakta, isliye real machines dono rakhti hain — dekho Memory hierarchy .
Register ek named slot hai jo ek single number hold karta hai jise ALU immediately read ya write kar sakta hai, bina kisi wait ke.
Picture: ek labelled cubby. MIPS-style code mein inhe R1, R2, R3, … likha jaata hai; ARM mein bhi yahi idea hai. Jab parent note ADD R6, R4, R5 likhta hai, toh padho:
"Worker: cubby R4 mein jo number hai woh lo, cubby R5 mein jo number hai woh lo, unhe add karo, jawab cubby R6 mein rakh do."
Note karo ki teeno naam cubbies hain, kabhi mailboxes nahi. Yahi load/store machine ka poora rule hai, aur ise hum §4 mein pakka karenge.
Definition Memory addressMemory address woh number hai jo mailbox par likha hota hai — lambi row mein uska ghar ka number. Hum ise hexadecimal (base 16) mein 0x prefix ke saath likhte hain, jaise 0x1000, kyunki addresses bade ho jaate hain aur hex compact hai.
Notation [R0] ya 0(R1) ka matlab hai "woh mailbox jiska number abhi us register mein baitha hai" — square brackets kehte hain "is number ko khud use mat karo, us mailbox par jao jis par yeh point karta hai."
0(R1) mein 0 ek offset hai — "R1 mein jo address hai wahan se shuru karo, phir 0 mailboxes aage badho." Offsets ek register ko poore array ko point karne deta hai; woh machinery Addressing modes ka topic hai.
R1 aur [R1] ko confuse karna
Yeh ek jaisa kyun lagta hai: dono mein R1 ka zikr hai.
Yeh ek jaisa kyun nahi hai: R1 = 0x1000 ka matlab number ek-hazaar-hex ho sakta hai, ya phir yeh ek address ho sakta hai. [R1] likhna kehta hai "R1 ek address hai — ise chase karo." ADD R2, R2, R1 mein number 0x1000 add hota hai; LDR R2, [R1] mailbox 0x1000 mein jo bhi hai woh fetch karta hai. Bilkul alag actions hain.
Yahan topic ka dil hai, aur ab iska har shabd pehle se defined hai.
Definition Load aur Store
Load (LW, LDR): ek number mailbox se cubby mein copy karo (memory → register).Store (SW, STR): ek number cubby se wapas mailbox mein copy karo (register → memory).
Yeh akele instructions hain jinhe wire chhone ki ijazat hai. ALU kabhi directly memory nahi chhoota.
Intuition Walled-garden rule phir seArithmetic hamesha sirf cubbies ke beech hoti hai. Agar koi number memory mein rehta hai, toh pehle aapko use ek cubby mein load karna hoga, phir compute karna hoga, phir jawab wapas store karna hoga. Teen alag trips. Yahi ek discipline hai jise RISC vs CISC philosophy "load/store" kehta hai aur isliye parent note ka ARM example teen instructions ka hai jabki x86 ek ka.
Recall Memory par seedha arithmetic kyun forbid hai?Kyunki memory access ek unpredictable number of ticks leta hai (fast agar number paas ho, slow agar door ho — dekho Memory hierarchy ). Saari us unpredictability ko sirf do instruction types mein quarantine karke, baaki har instruction fast ho jaati hai aur ek fixed, known time leti hai. ::: Predictable timing hi extra instructions ka inaam hai.
Instruction ek aisa command hai jise CPU ek single fetch-decode-execute cycle mein carry out kar sakta hai, jaise LDR R1, [R0]. Pehla shabd (LDR, ADD, SW) opcode hai — woh verb jo kehta hai kaun si operation karni hai.
Parent note instructions ko letter I
Definition Clock aur cycleCPU ek metronome ke saath chalta hai. Har tick ek clock cycle hai. Clock period T clk Frequency f clk = 1/ T clk
Topic ko frequency kyun chahiye: simpler instructions (§4 ka rule) chip ko har tick ka kaam jaldi khatam karne deta hai, toh T clk f clk
CPI = Cycles Per Instruction = average number of clock ticks jo har instruction khata hai.
CPI = number of instructions total clock cycles used
Intuition Latency vs throughput — wo subtle baat jis par parent lean karta haiEk akela load khud se 10 ticks le sakta hai (uski latency ). Lekin jab woh wait karta hai, pipeline doosri instructions kar rahi hoti hai. Toh instruction ke hisaab se average cost (CPI) 10 se kaafi kam ho sakta hai. Yahi overlap ki wajah se parent ko CPI ARM = 12/3 = 4
Parent mein symbol ≪ $\text{CPI}_{\text{ls}} \ll \text{CPI}_{\text{rm}}$) ka matlab sirf "bahut chhota hai" hai.
Ab har letter earn ho chuka hai, toh master equation saaf padhi jaati hai:
Chalte hain parent ke headline numbers ko sirf defined symbols se verify karte hain:
Worked example 4.0 ns ki tiex86: I = 1 , CPI = 10 , T clk = 0.4 ns T x86 = 1 × 10 × 0.4 = 4.0 ns ARM: I = 3 , CPI = 4 , T clk = 0.33 ns T ARM = 3 × 4 × 0.33 ≈ 4.0 ns
Parent ke Example 2 mein (a+b) aur (c+3) ek saath cubbies mein alive rehte hain. Agar cubbies khatam ho jayein toh aapko ek ko wapas memory mein dump karna padta hai (ek spill ) aur baad mein reload karna padta hai — extra slow trips. Isliye load/store machines 32 registers rakhti hain, 8 nahi. Kaunsi value kahan rahegi yeh choose karna Register allocation hai.
Memory - big slow mailboxes
Registers - tiny fast cubbies
ALU works on registers only
CPI cycles per instruction
Load-store performance argument
Khud ko test karo — har line ka right side dhako aur zyور se jawab do.
Register kya hold karta hai, aur yeh kitna fast hai?Ek number, instantly reachable (koi memory wait nahi).
[R1] ka matlab kya hai R1 ke mukable?[R1] = us mailbox ki value jiska address R1 mein hai; R1 = R1 ke andar ki value itself.
Load/store machine mein memory touch karne ki ijazat kaun se instructions ko hai? Sirf load aur store — kabhi arithmetic ko nahi.
Arithmetic kahan hoti hai? Poori tarah registers ke beech, ALU ke zariye.
Execution-time formula likho. T = I × CPI × T clk
f clk = 2.5 GHz T clk = 1/ ( 2.5 × 1 0 9 ) = 0.4 ns
CPI ko ek line mein define karo. Total clock cycles ÷ number of instructions (ek average).
CPI ek single instruction ki latency se kaafi kam kyun ho sakta hai? Pipelining waiting instructions ko useful kaam ke saath overlap karta hai.
Load/store ISAs mein zyada registers kyun hote hain? Intermediate values ko slow memory mein spill karne se bachne ke liye.
